公开(公告)号：US06982573B2

公开(公告)日：2006-01-03

申请号：US10827675

申请日：2004-04-19

Applicant: Matt Hutson ,  Andrew Dellow ,  Tom Ryan ,  Paul Elliott

Inventor： Matt Hutson ,  Andrew Dellow ,  Tom Ryan ,  Paul Elliott

IPC: H03K17/00

CPC classification number: G06F1/08

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

公开(公告)号：US20050055489A1

公开(公告)日：2005-03-10

申请号：US10658595

申请日：2003-09-09

Applicant: Paul Elliott

Inventor： Paul Elliott

IPC: G06F5/06 ,  G06F5/10 ,  G06F13/36

CPC classification number: G06F5/10 ,  G06F5/065

Abstract: A bridge circuit includes two FIFO circuits each having an associated FIFO control circuit. In each FIFO control circuit, a write pointer register and a read pointer register for controlling the storage location for writing to and reading from the FIFO circuit are each controlled by control logic. The control logic is responsive to comparators which receive and compare the write pointer value and the retimed read pointer value to control the write pointer register, and receive and compare the read pointer value and the retimed write pointer value to control the read pointer register. The retiming circuits are configurable in response to a mode signal to provide different degrees of retiming. The maximum number of storage locations that can be full at any one time is a fixed limit.

Abstract translation: 桥接电路包括两个FIFO电路，每个具有相关的FIFO控制电路。 在每个FIFO控制电路中，用于控制用于写入和读取FIFO电路的存储位置的写指针寄存器和读指针寄存器均由控制逻辑控制。 控制逻辑响应于比较器，其接收并比较写指针值和重定时读指针值以控制写指针寄存器，并且接收并比较读指针值和重定时写指针值以控制读指针寄存器。 重新定时电路可以响应于模式信号而配置，以提供不同程度的重新定时。 任何时间可以充满的存储位置的最大数量是固定的限制。

公开(公告)号：US06851237B2

公开(公告)日：2005-02-08

申请号：US10430960

申请日：2003-05-06

Applicant: Michael Niese ,  Paul Elliott

Inventor： Michael Niese ,  Paul Elliott

IPC: E04F15/04 ,  E04B5/02 ,  E04F15/14

CPC classification number: E04F15/048 ,  E04F15/04 ,  E04F2201/0153 ,  E04F2201/023 ,  E04F2201/025 ,  E04F2201/04

Abstract: A wood floor system comprises a plurality of parallel rows of floorboards laid end-to-end, and each of the floorboards includes a compression nub extending along a side surface thereof, adjacent the top surface. These compression nubs affirmatively engage an opposing side surface of an adjacent floorboard row, thereby sealing, or isolating, the top surface of the floor from the side surfaces of the floorboard rows. This uniformly distributes expansion and contraction forces throughout the floor, due to uniform spacing between the floorboard rows. The isolation of the upper floorboard surface from the side surface also prevents undesired downward migration or flow of liquid finishing solution, which can have serious adverse affects for a wood floor. The invention reduces the total volume of finishing solution necessary for finishing the floor, and it also reduces “overwood” during floor installation.

Abstract translation: 木地板系统包括多个平行排的地板，其一端至另一端设置，并且每个地板块包括沿着其侧表面延伸的邻近顶面的压缩空隙。 这些压缩凸块肯定地接合相邻地板块行的相对的侧表面，从而将地板的顶表面与地板块行的侧表面密封或隔离。 由于地板行之间的间隔均匀，这样一来在整个地板上均匀分布伸缩力。 上层板表面与侧面的隔离也可以防止液体整理液的不希望的向下移动或流动，这可能对木地板产生严重的不利影响。 本发明减少了整理地板所需的整理溶液的总体积，并且还减少了地板安装期间的“超硬”。

公开(公告)号：US06774681B2

公开(公告)日：2004-08-10

申请号：US10157731

申请日：2002-05-29

Applicant: Andrew Dellow ,  Paul Elliott

Inventor： Andrew Dellow ,  Paul Elliott

IPC: H03K1700

CPC classification number: G06F1/08

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract translation: 用于根据切换请求信号选择第一时钟信号A或第二时钟信号B的时钟源选择器包括三个重新定时电路，每个由两个时钟触发器组成。 开关请求信号相对于时钟A首先被重新定时以给出信号P，相对于时钟B被重新定时以给出信号Q，并且最后相对于时钟A被重新定时以给出信号R.选择器电路操作使得当 信号Q被置位，当第二时钟信号B被输出时，当由或非门组合的信号P和信号R都不被断言时，输出第一时钟信号A，并且在其它时间输出零电平。 时钟源选择器可用于集成电路中以形成无毛刺多路复用器。

公开(公告)号：US06256840B1

公开(公告)日：2001-07-10

申请号：US09370616

申请日：1999-08-07

Applicant: Paul Elliott

Inventor： Paul Elliott

IPC: A47K1002

CPC classification number: A63B57/60 ,  A63B47/04 ,  A63B2047/043 ,  Y10T24/13 ,  Y10T24/1391 ,  Y10T24/3449

Abstract: The present invention 10 discloses a clasped towel 10 wherein a towel 11 is attached to a clasp 13 which can be attached by means 30 to an article of clothing 12. A flap 38 is attached to the towel 11 which forms a partial pocket-like enclosure 39 on the towel in which items can be cleaned. An alligator clip-like element 32 is also shown for attaching the present invention 10 to the clothing 12.

Abstract translation: 本发明10公开了一种紧身毛巾10，其中毛巾11连接到可以通过装置30附接到衣服12的扣环13上。舌片38附接到毛巾11上，毛巾11形成部分袋状外壳 39在可以清洁物品的毛巾上。 还示出了鳄鱼夹状元件32用于将本发明10附接到衣服12。