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    NoC relaxed write order scheme
    1.
    发明授权
    NoC relaxed write order scheme 有权

    公开(公告)号：US11714779B2

    公开(公告)日：2023-08-01

    申请号：US16830142

    申请日：2020-03-25

    申请人： XILINX, INC.

    发明人： Abbas Morshed ,  Ygal Arbel ,  Eun Mi Kim

    IPC分类号： G06F15/78 ,  G06F5/10 ,  G06F9/38 ,  G06F13/40

    CPC分类号： G06F15/7825 ,  G06F5/10 ,  G06F9/38 ,  G06F13/4027 ,  G06F2205/064 ,  G06F2213/0038

    摘要： Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.

    METHOD FOR CYCLE ACCURATE DATA TRANSFER IN A SKEWED SYNCHRONOUS CLOCK DOMAIN
    2.
    发明申请
    METHOD FOR CYCLE ACCURATE DATA TRANSFER IN A SKEWED SYNCHRONOUS CLOCK DOMAIN 审中-公开

    公开(公告)号：US20190004564A1

    公开(公告)日：2019-01-03

    申请号：US15573917

    申请日：2016-06-14

    申请人： GYAN PRAKASH ,  NIDHIR KUMAR

    发明人： GYAN PRAKASH ,  NIDHIR KUMAR

    IPC分类号： G06F1/12

    CPC分类号： G06F1/12 ,  G06F1/04 ,  G06F5/06 ,  G06F5/10 ,  G06F9/30141 ,  G06F9/3869 ,  G06F2205/123 ,  G11C7/10 ,  G11C7/1093 ,  G11C7/22 ,  H03K19/20

    摘要： A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges w both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address resister. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.

    COMPARATOR AND MEMORY REGION DETECTION CIRCUITRY AND METHODS
    5.
    发明申请
    COMPARATOR AND MEMORY REGION DETECTION CIRCUITRY AND METHODS 审中-公开

    公开(公告)号：US20180074954A1

    公开(公告)日：2018-03-15

    申请号：US15681467

    申请日：2017-08-21

    申请人： ARM LIMITED

    发明人： Simon John CRASKE

    IPC分类号： G06F12/02 ,  G06F7/509 ,  G06F5/10

    CPC分类号： G06F12/0292 ,  G06F5/10 ,  G06F7/02 ,  G06F7/026 ,  G06F7/509 ,  G06F17/505 ,  G06F2207/382

    摘要： Comparator circuitry comprises carry-save-addition (CSA) circuitry to generate a set of partial sum bits and a set of carry bits in respect of corresponding bit positions in a first input value, a second input value, a carry-in value associated with the first and second input values, and a third input value, the CSA circuitry comprising inverter circuitry to provide a relative inversion between the third input value and the group consisting of the first and second input values; and combiner circuitry to combine the set of partial sum bits, the set of carry bits offset by a predetermined number of bits in a more significant bit direction, the carry-in value and 1, to generate at least a carry output bit; in which the carry output bit is indicative of whether the third input value is greater than the sum of the first and second input values.

    Search query user interface
    6.
    发明授权
    Search query user interface 有权

    公开(公告)号：US09836550B2

    公开(公告)日：2017-12-05

    申请号：US12145079

    申请日：2008-06-24

    申请人： Jack Chu ,  Chris Mancini ,  Lawrence Morrisroe

    发明人： Jack Chu ,  Chris Mancini ,  Lawrence Morrisroe

    IPC分类号： G06F3/048 ,  G06F17/30 ,  G06F3/14 ,  G06F5/10

    CPC分类号： G06F17/30899 ,  G06F3/048 ,  G06F3/1438 ,  G06F5/10

    摘要： In a client-server system where a client system presents a browser for user interaction, a browser user interface includes functionality for handling dynamic interface elements received by the browser in connection with received pages, presented as part of the browser user interface and modified in response to selected user input without requiring farther interaction with a server. In addition to, or in place of, dynamic interface elements such as slide sheets, the browser user interface might also include a rotation display area, tool displays that can overlay a page, opaquely or semi-transparently, menu structures, and an ability for the user to modify a page layout without requiring server interaction. The browser might comprise storage for a plurality of rotation display items for storing a summary and a primary presentation for each rotation display item, logic for displaying, by the browser, primary presentations for less all of the plurality of rotation display items in the rotation display area, logic for displaying, by the browser, summaries for items wherein the number of summaries is greater than the number of primary presentations presented at one time, logic for highlighting, among the summaries displayed, the ones of the summaries that correspond to the primary presentations displayed in the rotation display area; and logic for rotating the plurality of rotation display items to display primary presentations for a different subsets of the rotation display items and for updating highlighting of summaries to correspond to the different subsets of rotation display items.

    Polyphase buffer for rate-conversion
    8.
    发明授权
    Polyphase buffer for rate-conversion 有权

    公开(公告)号：US09715914B1

    公开(公告)日：2017-07-25

    申请号：US15259161

    申请日：2016-09-08

    申请人： Syntropy Systems, LLC

    发明人： Christopher Pagnanelli

    IPC分类号： G11C7/22

    CPC分类号： G11C7/222 ,  G06F5/10

    摘要： Provided are, among other things, systems, apparatuses methods and techniques for changing the sampling rate of a discrete-time signal. One such apparatus includes a plurality of parallel processing paths, with each path comprising multiple storage banks and multiplexing elements that operate at a subsampling rate.

    Multi-protocol configurable transceiver including configurable deskew in an integrated circuit
    10.
    发明授权
    Multi-protocol configurable transceiver including configurable deskew in an integrated circuit 有权
    多协议可配置收发器，包括集成电路中的可配置的偏移校正

    公开(公告)号：US09531646B1

    公开(公告)日：2016-12-27

    申请号：US12632744

    申请日：2009-12-07

    申请人： Divya Vijayaraghavan ,  Curt Wortman ,  Chong H. Lee ,  Vinson Chan

    发明人： Divya Vijayaraghavan ,  Curt Wortman ,  Chong H. Lee ,  Vinson Chan

    IPC分类号： G06F3/00 ,  H04L12/861 ,  G06F5/10

    CPC分类号： H04L49/90 ,  G06F5/10

    摘要： Embodiments include a configurable multi-protocol transceiver including configurable deskew circuitry. In one embodiment, configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. In another embodiment, configurable circuitry is adapted to control a deskew character transmit insertion frequency. In another embodiment, a programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. In another embodiment, configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations. In another embodiment, configurable selection circuitry allows deskew processing to occur in a data path either before or after clock compensation processing depending on a communication protocol for which the transceiver is to be configured.

    摘要翻译： 实施例包括可配置的多协议收发器，包括可配置的偏移电路。 在一个实施例中，可配置电路适于控制多个缓冲器的允许数据深度。 在另一个实施例中，可配置电路适于控制偏斜字符传输插入频率。 在另一个实施例中，可编程状态机适于根据用于实现对准锁定状态的可选条件来控制读取和写入指针。 在另一个实施例中，可配置电路适于在收发器中的逻辑和路由资源之间选择逻辑，并且在IC的核心中布线资源，其中实现收发器用于控制至少某些去歪斜操作。 在另一个实施例中，可配置的选择电路允许在时钟补偿处理之前或之后在数据路径中进行偏移处理，这取决于要配置收发器的通信协议。