公开(公告)号：US20150333118A1

公开(公告)日：2015-11-19

申请号：US14705057

申请日：2015-05-06

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Tetsuya IIDA ,  Akio ICHIMURA ,  Yuya ABIKO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7811 ,  H01L21/265 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66477 ,  H01L29/66712

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

Abstract translation: 提供包括具有提高的可靠性的功率半导体元件的半导体器件。 半导体器件具有形成在单元区域外的单元区域和周边区域。 使单元区域中的n型列区域的n型杂质浓度高于在外围区域中由外延层构成的n型列区域的n型杂质浓度。 此外，在单元区域和外围区域中的每一个中保持电荷平衡，并且设置每个总电荷，使得第一p型列区域的总电荷和单元区域中的n型列区域的总电荷 分别变得大于第三p型列区域的总电荷和由周边区域中的外延层构成的n型列区域。