公开(公告)号：US20180240905A1

公开(公告)日：2018-08-23

申请号：US15946060

申请日：2018-04-05

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Tetsuya IIDA ,  Akio ICHIMURA ,  Yuya ABIKO

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L21/265 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66477 ,  H01L29/66712

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

公开(公告)号：US20180158910A1

公开(公告)日：2018-06-07

申请号：US15869023

申请日：2018-01-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Satoshi EGUCHI ,  Akio ICHIMURA ,  Natsuo YAMAGUCHI ,  Tetsuya IIDA

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/08

CPC classification number: H01L21/38 ,  H01L21/76237 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/0688 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66727 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7811

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

公开(公告)号：US20160268369A1

公开(公告)日：2016-09-15

申请号：US14968004

申请日：2015-12-14

Applicant: Renesas Electronics Corporation

Inventor： Akio ICHIMURA ,  Satoshi EGUCHI ,  Tetsuya IIDA ,  Yuya ABIKO

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7811

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

Abstract translation: 形成具有高纵横比的超结结构。 外延层使用沟槽填充工艺分层地形成，并且当已经形成每个层时，在该层中形成沟槽。 例如，当已经形成第一外延层时，在外延层中形成第一沟槽。 随后，当已经形成第二外延层时，在外延层中形成第二沟槽。 随后，当形成第三外延层时，在第三外延层中形成第三沟槽。

公开(公告)号：US20180012959A1

公开(公告)日：2018-01-11

申请号：US15700669

申请日：2017-09-11

Applicant: Renesas Electronics Corporation

Inventor： Akio ICHIMURA ,  Satoshi EGUCHI ,  Tetsuya IIDA ,  Yuya ABIKO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7811

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

公开(公告)号：US20160204192A1

公开(公告)日：2016-07-14

申请号：US14965899

申请日：2015-12-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Satoshi EGUCHI ,  Akio ICHIMURA ,  Natsuo YAMAGUCHI ,  Tetsuya IIDA

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/0696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/0688 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66727 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7811

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract translation: 在包括p型列和n型列周期性排列的超结结构的半导体器件中，形成半导体元件的单元区域中的p型列区的深度比深度 在围绕细胞区域的中间区域中的p型列区域。 由此，电池区域的击穿电压变得低于中间区域的击穿电压。 即使在产生雪崩电流的电池区域中，优先发生雪崩击穿现象，电流分散而平稳地流动。 由此，能够避免局部的电流收缩和附带的断线，能够提高雪崩电阻（半导体装置的崩溃电流量的破坏）。

公开(公告)号：US20160049466A1

公开(公告)日：2016-02-18

申请号：US14826075

申请日：2015-08-13

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Akio ICHIMURA ,  Toshiaki IGARASHI ,  Yasuhiro SHIRAI

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/045 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/7827

Abstract: To improve characteristics of a semiconductor device (vertical power MOSFET). A spiral p-type column region having a corner is formed in a peripheral region surrounding a cell region in which a semiconductor element is formed. In an epitaxial layer of the peripheral region surrounding the cell region in which the semiconductor element is formed, a trench spirally surrounding the cell region and having the first and second side faces making up the corner is formed and the trench is filled with the epitaxial layer. By spirally arranging the p-type column region (n-type column region) in such a manner, a drop in a withstand voltage margin due to a hot spot can be avoided. In addition, the continuity of the p-type column region (n-type column region) is maintained. As a result, electric field concentration is alleviated step by step toward the outer periphery and the withstand voltage is therefore increased.

Abstract translation: 改善半导体器件（垂直功率MOSFET）的特性。 在围绕形成有半导体元件的单元区域的周边区域中形成具有角部的螺旋状p型列区域。 在围绕形成有半导体元件的单元区域的外围区域的外延层中，形成螺旋状包围单元区域并且具有构成拐角的第一和第二侧面的沟槽，并且沟槽被外延层填充 。 通过以这种方式螺旋地排列p型列区域（n型列区域），可以避免由于热点导致的耐受电压裕度的下降。 此外，保持p型列区域（n型列区域）的连续性。 结果，逐渐朝向外周逐渐减小电场浓度，耐压提高。

公开(公告)号：US20150333118A1

公开(公告)日：2015-11-19

申请号：US14705057

申请日：2015-05-06

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Tetsuya IIDA ,  Akio ICHIMURA ,  Yuya ABIKO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7811 ,  H01L21/265 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66477 ,  H01L29/66712

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

Abstract translation: 提供包括具有提高的可靠性的功率半导体元件的半导体器件。 半导体器件具有形成在单元区域外的单元区域和周边区域。 使单元区域中的n型列区域的n型杂质浓度高于在外围区域中由外延层构成的n型列区域的n型杂质浓度。 此外，在单元区域和外围区域中的每一个中保持电荷平衡，并且设置每个总电荷，使得第一p型列区域的总电荷和单元区域中的n型列区域的总电荷 分别变得大于第三p型列区域的总电荷和由周边区域中的外延层构成的n型列区域。