公开(公告)号：US10381369B2

公开(公告)日：2019-08-13

申请号：US15841644

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsoo Kim ,  Hyunmog Park ,  Joongshik Shin

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/06 ,  H01L21/822 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A vertical memory device structure can include a vertical channel structure that vertically penetrates through an upper structure and a lower structure of a stack structure in a cell array region of the device. The vertical channel structure can have a side wall with a stepped profile at a level in the vertical channel structure where the upper structure meets the lower structure. A vertical dummy structure can vertically penetrate through a staircase structure that is defined by the upper structure and the lower structure in a connection region of the device, and the vertical dummy structure can have a side wall with a planar profile at the level where the upper structure meets the lower structure.