公开(公告)号：US20200161462A1

公开(公告)日：2020-05-21

申请号：US16688974

申请日：2019-11-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40

Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

公开(公告)号：US20190229203A1

公开(公告)日：2019-07-25

申请号：US16254322

申请日：2019-01-22

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/20 ,  H01L21/324 ,  H01L21/225 ,  H01L29/778

Abstract: A manufacturing method of an HEMT includes: forming a heterostructure; forming a first gate layer of intrinsic semiconductor material on the heterostructure; forming a second gate layer, containing dopant impurities of a P type, on the first gate layer; removing first portions of the second gate layer so that second portions, not removed, of the second gate layer form a doped gate region; and carrying out a thermal annealing of the doped gate region so as to cause a diffusion of said dopant impurities of the P type in the first gate layer and in the heterostructure, with a concentration, in the heterostructure, that decreases as the lateral distance from the doped gate region increases.

公开(公告)号：US20180358458A1

公开(公告)日：2018-12-13

申请号：US16004272

申请日：2018-06-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando IUCOLANO ,  Giuseppe GRECO ,  Fabrizio ROCCAFORTE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7378

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.