公开(公告)号：US20140017821A1

公开(公告)日：2014-01-16

申请号：US13932134

申请日：2013-07-01

Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L25/07

CPC classification number: H01L25/07 ,  H01L27/0262 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well.

Abstract translation: 集成电路包括四个电子部件，在电子部件下方并且铅垂的埋入的UTBOX层和在层下方具有相应部件的两对相对掺杂的接地平面。 第一隔离沟槽将接地层与相应的铅垂阱相分离并与接地层接触并呈现出第一掺杂型。 偏置电极接触相应的阱和接地层。 一对电极用于连接到第一偏置电压，另一对电极用于连接到第二偏置电压。 还包括呈现第一类掺杂的半导体衬底和呈现第二类掺杂的深埋阱。 深埋的井与其他井接触并将其与基底分离。 最后，控制电极耦合到深埋井。