公开(公告)号：US12094798B2

公开(公告)日：2024-09-17

申请号：US17618886

申请日：2019-08-26

Applicant: Mitsubishi Electric Corporation

Inventor： Hiroshi Kobayashi ,  Tomohisa Yamane ,  Shinnosuke Soda

IPC: H01L23/367 ,  H01L21/02 ,  H01L23/00 ,  H01L23/10 ,  H01L23/31 ,  H01L23/36 ,  H01L23/46 ,  H01L25/07

CPC classification number: H01L23/36 ,  H01L21/02304 ,  H01L23/10 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/46 ,  H01L24/26 ,  H01L25/07 ,  H01L2924/181

Abstract: Provided is a semiconductor device that prevents resin from leaking out from a resin insulating member at a periphery of the resin insulating member and thereby achieves an increase in reliability. The semiconductor device includes a module unit, a resin insulating member bonded to the module unit, a cooling unit coupled to the module unit with the resin insulating member interposed therebetween, and a flow blocking member disposed between the module unit and the cooling unit to surround the resin insulating member, the flow blocking member being more easily compressively deformable than the resin insulating member.

公开(公告)号：US11967543B2

公开(公告)日：2024-04-23

申请号：US18052456

申请日：2022-11-03

Applicant: ROHM CO., LTD.

Inventor： Toshio Hanada

IPC: H01L23/482 ,  H01L21/50 ,  H01L21/56 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H01L25/07 ,  H01L25/11 ,  H01L25/18 ,  H02M7/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/482 ,  H01L21/50 ,  H01L21/565 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/538 ,  H01L25/07 ,  H01L25/072 ,  H01L25/115 ,  H01L25/18 ,  H02M7/003 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/207 ,  H01L2924/30107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2924/12032 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.

公开(公告)号：US11798892B2

公开(公告)日：2023-10-24

申请号：US17149670

申请日：2021-01-14

Applicant: Intel Corporation

Inventor： John S. Guzek

IPC: H01L23/538 ,  H01L23/13 ,  H01L21/56 ,  H01L23/498 ,  H01L25/07 ,  H01L25/065 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/568 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/07 ,  H01L23/3128 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/18161

Abstract: Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.

公开(公告)号：US11675957B2

公开(公告)日：2023-06-13

申请号：US17319687

申请日：2021-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Feng Wei Kuo ,  Shuo-Mao Chen ,  Chin-Yuan Huang ,  Kai-Yun Lin ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

IPC: G06F30/398 ,  H01L23/544 ,  H01L25/07

CPC classification number: G06F30/398 ,  H01L23/544 ,  H01L25/07 ,  H01L2223/54426

Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.

公开(公告)号：US20190221549A1

公开(公告)日：2019-07-18

申请号：US16360341

申请日：2019-03-21

Applicant: DENSO CORPORATION

Inventor： Hiromasa HAYASHI ,  Shunsuke TOMOTO ,  Yusuke MORI

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L23/40 ,  G01R19/00 ,  G01R15/14

CPC classification number: H01L25/072 ,  G01R15/146 ,  G01R19/0092 ,  H01L23/3121 ,  H01L23/4006 ,  H01L23/48 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/07 ,  H01L25/18 ,  H01L2023/4031 ,  H01L2023/4087 ,  H01L2224/40137 ,  H01L2224/45111 ,  H01L2224/45147 ,  H01L2224/45149 ,  H01L2224/45155 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/18301

Abstract: A semiconductor device includes: a first chip to restrict current flow in a first direction through a current path; a second chip to restrict the current flow in a second direction opposite to the first direction, through the current path; a wiring having one end connected to the first chip and the other end connected to the second chip, and provided as a part of the current path by relaying the first chip and the second chip; a lead frame having a first lead arranged and fixed with the first chip and a second lead is arranged and fixed with the second chip; and molding resin sealing the first chip, the second chip, the wiring and the lead frame. The wiring is a shunt resistor having a resistive body. The lead frame further has a sense terminal to detect a voltage drop across the resistive body.

公开(公告)号：US20190198428A1

公开(公告)日：2019-06-27

申请号：US16254049

申请日：2019-01-22

Applicant: WASEDA UNIVERSITY

Inventor： Kohei Tatsumi

IPC: H01L23/482 ,  H01L23/12 ,  H01L23/492 ,  H01L25/07 ,  H01L23/367 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/482 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/12 ,  H01L23/367 ,  H01L23/492 ,  H01L25/07 ,  H01L25/072 ,  H01L25/18 ,  H01L25/50

Abstract: A power semiconductor module device includes: a plurality of semiconductor elements that are arranged at intervals and flush with each other on a plane; an insulating support that fixes the semiconductor elements; a first thick-film plating layer that is formed as a first-surface-side electrode that electrically connects the semiconductor elements to each other on at least one surface of a front surface side and a rear surface side. The first thick-film plating layer supports the semiconductor elements from at least one of an upper direction and a lower direction.

公开(公告)号：US20190193211A1

公开(公告)日：2019-06-27

申请号：US16277906

申请日：2019-02-15

Applicant: Lenovo (Singapore) Pte. Ltd.

Inventor： Ko Inaba ,  Tetsu Takemasa ,  Tadashi Kosuga

IPC: B23K35/26 ,  B23K1/00 ,  C22C12/00 ,  C22C13/02 ,  H01L25/07 ,  H01L25/18 ,  H05K3/34

CPC classification number: B23K35/26 ,  B23K1/00 ,  C22C12/00 ,  C22C13/00 ,  C22C13/02 ,  H01L25/07 ,  H01L25/18 ,  H05K3/34 ,  H05K3/3463

Abstract: A solder bonding method that bonds, using a solder joint, an electrode of a circuit board to an electrode of an electronic component includes: depositing, on the electrode of the circuit board, an Sn—Bi-based solder alloy with a lower melting point than a solder alloy deposited on the electrode of the electronic component; mounting the electronic component on the circuit board such that the Sn—Bi-based solder alloy contacts the solder alloy on the electrode of the electronic component; heating the circuit board to a peak temperature of heating of 150° C. to 180° C.; holding the peak temperature of heating at a holding time of greater than 60 seconds and less than or equal to 150 seconds; and cooling, after the heating and to form the solder joint, the circuit board at a cooling rate greater than or equal to 3° C./sec.

公开(公告)号：US20190189538A1

公开(公告)日：2019-06-20

申请号：US16095461

申请日：2016-09-09

Applicant: Mitsubishi Electric Corporation

Inventor： Shigeto FUJITA ,  Tetsuya MATSUDA

IPC: H01L23/48 ,  H01L25/07 ,  H01R11/01 ,  H01L29/20

CPC classification number: H01L23/481 ,  H01L23/48 ,  H01L25/07 ,  H01L25/074 ,  H01L25/18 ,  H01L29/2003 ,  H01R11/01

Abstract: A lower electrode, a semiconductor chip provided on the lower electrode, a pressure pad provided above or below the semiconductor chip, an upper electrode provided on a structure in which the pressure pad is overlapped with the semiconductor chip, and a connection conductor that provides a new current path between the lower electrode and the upper electrode only when a distance between the lower electrode and the upper electrode becomes larger than a predetermined value are provided. The distance between the lower electrode and the upper electrode is variable, and the pressure pad electrically connects the lower electrode and the upper electrode together via the semiconductor chip regardless of the distance between the lower electrode and the upper electrode.

公开(公告)号：US20190052189A1

公开(公告)日：2019-02-14

申请号：US16076444

申请日：2017-01-18

Applicant: SUMITOMO ELECTRIC INDUSTRIES., LTD.

Inventor： Hirotaka OOMORI

IPC: H02M7/537 ,  H02M1/34 ,  H01L25/18

CPC classification number: H02M7/537 ,  H01L25/07 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H02M1/32 ,  H02M1/34 ,  H02M7/003 ,  H02M7/48 ,  H02M7/5387 ,  H02M2001/348 ,  H01L2924/00014

Abstract: A semiconductor module according to an embodiment includes an insulating substrate having a power conversion circuit mounted thereon, a first transistor constituting an upper arm, a second transistor constituting a lower arm, a first input interconnection pattern coupled to a positive-side input terminal, a second input interconnection pattern coupled to a negative-side input terminal, an output interconnection pattern coupled to an output terminal, and an absorbing device configured to absorb surge voltage, wherein the first input interconnection pattern includes a first-transistor mounting area on which the first transistor is mounted, wherein the output interconnection pattern includes a second-transistor mounting area on which the second transistor is mounted, wherein the second input interconnection pattern includes an absorbing-device connecting area disposed between the first and second transistor mounting areas, and wherein the absorbing-device connecting area is electrically coupled to the first-transistor mounting area through the absorbing device.

公开(公告)号：US20190051602A1

公开(公告)日：2019-02-14

申请号：US16157933

申请日：2018-10-11

Applicant: Longitude Licensing Limited

Inventor： Akihiko Hatasawa

IPC: H01L23/538 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/53228 ,  H01L24/11 ,  H01L24/17 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/07 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012

Abstract: One semiconductor chip includes a substrate having insulation properties, a plurality of bump electrodes provided on one surface of the substrate, a plurality of recesses provided in the other surface of the substrate, and a solder layer disposed within the recesses. The recesses are formed such that the area of the opening decreases from the other surface side toward the one surface side of the substrate.