公开(公告)号：US20220059571A1

公开(公告)日：2022-02-24

申请号：US17200179

申请日：2021-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Baek ,  Jungho Do ,  Jaewoo Seo ,  Jisu Yu

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/48

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

公开(公告)号：US10861967B2

公开(公告)日：2020-12-08

申请号：US16819823

申请日：2020-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho Do

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L27/24

Abstract: A cell architecture is provided. A cell architecture including a vertical field effect transistor (VFET) having at least two fins serving as a vertical channel, a gate including a first gate portion surrounding the first fin, a second gate portion surrounding the second fin, and a third gate portion providing connection therebetween, and a top source/drain (S/D) including a first top S/D portion on the first fin and a second top S/D portion on the second fin, a gate contact structure connected to the third gate portion, a top S/D contact structure connected to one of the first top S/D portion or the second top S/D portion and serving as a horizontal conductive routing layer; and metal patterns on the gate contact structure and the top S/D contact structure and connected thereto through vias, and serving as a vertical conductive routing layer may be provided.