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1.发明公开公开(公告)号：US20230290779A1
公开(公告)日：2023-09-14
申请号：US18175765
申请日：2023-02-28
发明人： Jungho Do
IPC分类号： H01L27/092 , H01L23/48 , H01L29/78 , H01L29/423 , H01L29/06
CPC分类号： H01L27/0924 , H01L23/481 , H01L29/7851 , H01L29/42392 , H01L29/0673
摘要： An integrated circuit includes: (i) a first transistor having a first gate extending in a first direction, a first drain, and a first source that is separated from the first drain in a second direction, which is perpendicular to the first direction, (ii) a second transistor having a second gate extending in one of the first and second directions, a second drain, and a second source that is separated from the second drain in a third direction, which is perpendicular to the first and second directions, and (iii) a first connection structure that electrically connects the first transistor to the second transistor, and includes a pattern extending in the first direction between the first transistor and the second transistor.
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公开(公告)号：US20220058326A1
公开(公告)日：2022-02-24
申请号：US17183630
申请日：2021-02-24
发明人： Bonghyun Lee , Jungho Do
IPC分类号： G06F30/392 , H01L27/02 , H01L23/528
摘要： An integrated circuit includes a first column including a plurality of first cells aligned and placed in a plurality of first rows, each first row having a first width and extending in a first horizontal direction, a second column including a plurality of second cells aligned and placed in a plurality of second rows, each second row having a second width and extending in the first horizontal direction, and an interface column extending in a second horizontal direction perpendicular to the first horizontal direction between the first column and the second column, wherein the interface column includes at least one well tap configured to provide a first supply voltage to a well, and at least one substrate tap configured to provide a second supply voltage to a substrate.
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公开(公告)号：US20200220548A1
公开(公告)日：2020-07-09
申请号：US16820835
申请日：2020-03-17
发明人： Taejoong SONG , Jungho Do , Seungyoung Lee , Jonghoon Jung
IPC分类号： H03K19/17724 , H01L27/02 , H01L29/06 , H01L23/528 , H01L29/423 , H01L27/088
摘要： A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.
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4.发明公开公开(公告)号：US20240363532A1
公开(公告)日：2024-10-31
申请号：US18626985
申请日：2024-04-04
发明人： Seungyoung Lee , Jungho Do
IPC分类号： H01L23/528 , H01L23/522 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L23/5283 , H01L23/5226 , H01L27/092 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： An integrated circuit includes a standard cell including a first transistor and a second transistor each disposed on a front side of a substrate, a backside via passing through the substrate in a vertical direction with respect to the substrate, a backside wiring layer including a backside power rail disposed on a backside of the substrate and connected with a first source/drain of the first transistor through the backside via, and a backside contact extending in a first direction between the standard cell and the backside wiring layer and electrically connecting a second source/drain of the first transistor with a first source/drain of the second transistor, wherein a bottom level of the backside contact differs from a top level of the backside power rail, and the backside contact is electrically insulated from the backside power rail.
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公开(公告)号：US12068315B2
公开(公告)日：2024-08-20
申请号：US17323707
申请日：2021-05-18
发明人： Jungho Do , Sanghoon Baek
IPC分类号： H01L27/06 , H01L23/50 , H01L23/522 , H01L27/088 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0886 , H01L23/50 , H01L23/5226 , H01L27/0688 , H01L29/6681 , H01L29/785
摘要： A semiconductor device is provided. The semiconductor device includes a substrate including a first dummy region and a second dummy region spaced apart from the first dummy region; a device isolation layer filling a trench between the first dummy region and the second dummy region; a first dummy electrode provided on the first dummy region; a second dummy electrode provided on the second dummy region; a power line extending from the first dummy region to the second dummy region, the power line including an expanded portion provided on the device isolation layer, a width of the expanded portion being larger than a line width of a remaining portion of the power line; a power delivery network provided on a bottom surface of the substrate; and a through via extending through the substrate and the device isolation layer, and electrically connecting the power delivery network to the expanded portion. The through via and the expanded portion vertically overlap.
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6.发明公开公开(公告)号：US20230290784A1
公开(公告)日：2023-09-14
申请号：US18175696
申请日：2023-02-28
发明人： Jungho Do , Jisu Yu , Hyeongyu You , Yunkyeong Jang , Minjae Jeong
IPC分类号： H01L27/118 , H01L27/02
CPC分类号： H01L27/11807 , H01L27/0207 , H01L2027/11809
摘要： An integrated circuit may include a first active pattern group extending in a first direction in a first row and including a plurality of first active patterns overlapping each other in the first direction, the first row extending in the first direction, and a plurality of gate electrodes extending in a second direction perpendicular to the first direction in the first row. The plurality of first active patterns may include any two first active patterns that are adjacent to each other in the first direction, the two first active patterns have first and second widths in the second direction, respectively, and the first and second widths are identical or are different by a first offset or a second offset.
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7.发明申请公开(公告)号：US20220344463A1
公开(公告)日：2022-10-27
申请号：US17719996
申请日：2022-04-13
发明人： Hakchul Jung , Myunggil Kang , Jungho Do , Sanghoon Baek
IPC分类号： H01L29/06 , H01L27/088 , H01L29/786 , H01L23/48
摘要： An integrated circuit may include a first cell and a second cell. The first cell includes a first transistor in which nanosheets included in a first nanosheet stack and a second nanosheet stack extend in a first direction to pass through a first gate electrode that extends in a second direction intersecting with the first direction. The second cell includes a second transistor in which one or more nanosheets included in a third nanosheet stack extends in the first direction to pass through a second gate electrode that extends in the second direction. A length of the first cell in the second direction may be greater than a length of the second cell in the second direction.
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8.发明申请公开(公告)号：US20220262786A1
公开(公告)日：2022-08-18
申请号：US17670626
申请日：2022-02-14
发明人： Jisu Yu , Jungho Do , Jaewoo Seo , Hyeongyu You , Minjae Jeong
IPC分类号： H01L27/02 , H01L27/118
摘要： An integrated circuit including a first standard cell placed continuously on a row having a first height and a row having a second height different from the first height. The integrated circuit also includes a second standard cell continuously placed on a row having the first height and a row having the second height, a plurality of first power lines formed on boundaries of the plurality of rows and configured to supply a first supply voltage to the standard cells, and a plurality of second power lines formed on boundaries of the plurality of rows and configured to supply a second supply voltage to the standard cells. A placement sequence of the power lines supplying a voltage to the first standard cell being different from a placement sequence of the power lines supplying a voltage to the second standard cell.
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公开(公告)号：US12131999B2
公开(公告)日：2024-10-29
申请号：US18512527
申请日：2023-11-17
发明人： Jungho Do , Sanghoon Baek
IPC分类号： H01L23/528 , H01L27/02 , H01L27/092 , H01L29/423 , H01L29/786
CPC分类号： H01L23/5286 , H01L27/0207 , H01L27/092 , H01L29/42392 , H01L29/78696
摘要： A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.
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公开(公告)号：US12034008B2
公开(公告)日：2024-07-09
申请号：US18336754
申请日：2023-06-16
发明人： Sanghoon Baek , Jungho Do , Jaewoo Seo , Jisu Yu
IPC分类号： H01L27/02 , H01L23/48 , H01L27/118
CPC分类号： H01L27/11807 , H01L23/481 , H01L27/0207 , H01L2027/11829 , H01L2027/11864 , H01L2027/11881
摘要： A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.
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