-
公开(公告)号:US08327120B2
公开(公告)日:2012-12-04
申请号:US11967145
申请日:2007-12-29
IPC分类号: G06F7/38
CPC分类号: G06F9/30014 , G06F9/30094 , G06F9/30185 , G06F9/30189
摘要: Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control register may be overridden on a per instruction basis. In an embodiment, at least one of the one or more floating point operation settings is to cause a modification to one of the one or more default settings during execution of the instruction, wherein the second logic is to perform the floating point operation, at least in part, based on the modified default setting. Other embodiments are also described.
摘要翻译: 描述与浮点控制超控的指令有关的方法和装置。 在一个实施例中,由浮点控制寄存器指示的浮点运算设置可以在每个指令的基础上被覆盖。 在一个实施例中,所述一个或多个浮点运算设置中的至少一个是在执行指令期间对所述一个或多个默认设置之一进行修改,其中所述第二逻辑至少执行所述浮点运算 部分基于修改的默认设置。 还描述了其它实施例。
-
公开(公告)号:US20060294177A1
公开(公告)日:2006-12-28
申请号:US11166140
申请日:2005-06-27
申请人: Simon Rubanovich
发明人: Simon Rubanovich
IPC分类号: G06F7/52
CPC分类号: G06F7/535 , G06F2207/5356
摘要: Embodiments of the present invention provide a method, apparatus and system of dividing a first number by a second number. Some demonstrative embodiments include generating a first value relating to the first number; generating a second value corresponding to a remainder of a division of the number one by the second number; and dividing the first value by the second value. Some demonstrative embodiments include generating a plurality of independent interim values by adding at least first and second sets of one or more carry bits of an encoded remainder value corresponding to a cycle of a division operation to at least first and second sets of one or more sum bits of the encoded remainder value, respectively; and generating a plurality of coefficients corresponding to a quotient digit of the cycle based on the plurality of interim values. Other embodiments are described and claimed.
摘要翻译: 本发明的实施例提供一种将第一数量除以第二数量的方法,装置和系统。 一些说明性实施例包括生成与第一数字有关的第一值; 产生对应于第一个数除数的余数的第二个值; 并将第一个值除以第二个值。 一些说明性实施例包括通过将对应于除法运算的循环的编码余数值的一个或多个进位中的至少第一组和第二组相加至一个或多个总和的至少第一组和第二组来生成多个独立中间值 分别编码余数值的位; 以及基于所述多个临时值生成与所述周期的商数相对应的多个系数。 描述和要求保护其他实施例。
-
公开(公告)号:US20130067204A1
公开(公告)日:2013-03-14
申请号:US13670326
申请日:2012-11-06
IPC分类号: G06F9/302
CPC分类号: G06F9/30014 , G06F9/30094 , G06F9/30185 , G06F9/30189
摘要: Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control register may be overridden on a per instruction basis. Other embodiments are also described.
摘要翻译: 描述与浮点控制超控的指令有关的方法和装置。 在一个实施例中,由浮点控制寄存器指示的浮点运算设置可以在每个指令的基础上被覆盖。 还描述了其它实施例。
-
公开(公告)号:US20090172355A1
公开(公告)日:2009-07-02
申请号:US11967145
申请日:2007-12-29
IPC分类号: G06F9/44
CPC分类号: G06F9/30014 , G06F9/30094 , G06F9/30185 , G06F9/30189
摘要: Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control register may be overridden on a per instruction basis. Other embodiments are also described.
摘要翻译: 描述与浮点控制超控的指令有关的方法和装置。 在一个实施例中,由浮点控制寄存器指示的浮点运算设置可以在每个指令的基础上被覆盖。 还描述了其它实施例。
-
-
-