公开(公告)号：US09753693B2

公开(公告)日：2017-09-05

申请号：US14208591

申请日：2014-03-13

申请人： Imagination Technologies Limited

发明人： Thomas Rose

IPC分类号： G06F7/52 ,  G06F7/523 ,  G06F7/535 ,  G06F7/499 ,  G06F17/50

CPC分类号： G06F7/49947 ,  G06F7/4824 ,  G06F7/52 ,  G06F7/523 ,  G06F7/535 ,  G06F7/722 ,  G06F7/727 ,  G06F17/505 ,  G06F2207/5356

摘要： A binary logic circuit is provided for determining a rounded value of px q , where p and q are coprime constant integers with p

公开(公告)号：US20160110161A1

公开(公告)日：2016-04-21

申请号：US14519787

申请日：2014-10-21

申请人： ARM LIMITED

发明人： David Raymond LUTZ ,  Neil BURGESS

IPC分类号： G06F7/485

CPC分类号： G06F7/485 ,  G06F7/483 ,  G06F7/535 ,  G06F7/5525 ,  G06F7/57 ,  G06F2207/48 ,  G06F2207/5356

摘要： A data processing apparatus has floating-point add circuitry for performing a floating-point add operation for adding or subtracting two floating-point operands. The apparatus also has reciprocal estimation circuitry for performing a reciprocal estimation operation on a first operand to generate a reciprocal estimate value which represents an estimate of a reciprocal of a first operand or an estimate or a reciprocal of the square root of the first operand. The reciprocal estimation circuitry is physically distinct from the floating-point adder circuitry, which allows both the reciprocal estimate and the add operations to be faster.

摘要翻译： 数据处理装置具有用于执行用于相加或减去两个浮点操作数的浮点加法运算的浮点加法电路。 该装置还具有相互估计电路，用于对第一操作数执行倒数估计操作，以产生表示第一操作数的倒数的估计或第一操作数的平方根的倒数的倒数的倒数估计值。 相互估计电路在物理上不同于浮点加法器电路，这允许相互估计和相加操作都更快。

公开(公告)号：US08775494B2

公开(公告)日：2014-07-08

申请号：US13038193

申请日：2011-03-01

申请人： Alexandru Fit-Florea

发明人： Alexandru Fit-Florea

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/4873 ,  G06F7/49942 ,  G06F7/5525 ,  G06F2207/5355 ,  G06F2207/5356

摘要： A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case.

摘要翻译： 公开了一种用于执行浮点计算的计算机实现的方法，其中相关联的结果的精确值不能被表示为浮点值。 该方法包括：产生关联结果的估计并将估计存储在存储器中; 计算估计的误差量; 确定误差量是否小于或等于相关结果的误差阈值; 并且如果误差量小于或等于误差阈值，则认为相关结果的估计是浮点计算的正确舍入结果; 或者如果错误量大于错误阈值，则测试浮点计算是否构成异常情况。

公开(公告)号：US08352534B2

公开(公告)日：2013-01-08

申请号：US12326181

申请日：2008-12-02

申请人： Chen-Hung Chan

发明人： Chen-Hung Chan

IPC分类号： G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/5356

摘要： An integer division circuit with allowable error is described, what a signal processing apparatus includes a pointer, a first left shifter, a second left shifter, a subtractor, a multiplier, and a right shifter. The pointer searches for a most significant non-zero bit of a divisor and outputs a most significant byte value. The first left shifter performs a shift operation according to the most significant byte value, so as to generate a first exponential coefficient. The second left shifter performs a shift operation according to the most significant byte value, so as to generate a second exponential coefficient. The subtractor calculates a multiplier factor according to the divisor, the first exponential coefficient, and the second exponential coefficient and outputs the multiplier factor to the multiplier. The multiplier multiplies an input value with the multiplier factor and outputs a result to the right shifter. The right shifter outputs a calculation result.

摘要翻译： 描述了具有允许误差的整数除法电路，信号处理装置包括指针，第一左移位器，第二左移位器，减法器，乘法器和右移位器。 指针搜索除数的最重要的非零位，并输出最高有效字节值。 第一左移位器根据最高有效字节值执行移位操作，以便产生第一指数系数。 第二左移位器根据最高有效字节值执行移位操作，以产生第二指数系数。 减法器根据除数，第一指数系数和第二指数系数计算乘数，并将乘数作为乘数输出。 乘法器将输入值乘以乘数，并将结果输出到右移位器。 右移位器输出计算结果。

公开(公告)号：US07962543B2

公开(公告)日：2011-06-14

申请号：US11756885

申请日：2007-06-01

申请人： Michael J. Schulte ,  Carl E. Lemonds, Jr. ,  Dimitri Tan

发明人： Michael J. Schulte ,  Carl E. Lemonds, Jr. ,  Dimitri Tan

IPC分类号： G06F7/535

CPC分类号： G06F7/4873 ,  G06F2207/5356

摘要： A division method includes determining a precision indicator for the division operation that indicates whether the quotient should be a single precision, double precision, or extended precision floating-point number. The division is performed at a rectangular multiplier using the Goldschmidt or Newton-Raphson algorithm. Each algorithm calculates one or more intermediate values in order to determine the quotient. For example, the Goldschmidt algorithm calculates a complement of a product of the dividend and an estimate of the reciprocal of the divisor. The quotient is determined based on a portion of one or more of these intermediate values. Because only a portion of the intermediate value is used, the division can be performed efficiently at the rectangular multiplier, and therefore the quotient can be determined more quickly and still achieve the desired level of precision.

摘要翻译： 分割方法包括确定用于指示商是否应当是单精度，双精度或扩展精度浮点数的除法运算的精度指示符。 使用Goldschmidt或Newton-Raphson算法在矩形乘法器上执行除法。 每个算法计算一个或多个中间值以确定商。 例如，Goldschmidt算法计算股息的乘积的互补和除数的倒数的估计。 基于这些中间值中的一个或多个的一部分来确定商。 因为仅使用中间值的一部分，所以可以在矩形乘法器上有效地执行除法，因此可以更快速地确定商并且仍然达到期望的精度水平。

公开(公告)号：US20100289837A1

公开(公告)日：2010-11-18

申请号：US12844848

申请日：2010-07-28

申请人： Tien-Chu Hsu

发明人： Tien-Chu Hsu

IPC分类号： G09G5/10

CPC分类号： G06F7/53 ,  G06F7/49921 ,  G06F7/535 ,  G06F2207/5356 ,  G09G3/3611 ,  G09G5/10 ,  G09G2320/0646 ,  G09G2360/16

摘要： A division unit, an image analysis unit and a display apparatus using the same capable of simplifying the computation of overall average gray scale are provided. The division unit includes an adder for receiving a first to an Nth bus signals to produce an addition result, wherein the first to the Nth bus signals shift the input signal by a different number of bits and adding logic zeros to the shifted bits as compensation, where N is a positive whole number, and a multiplexer for receiving a most significant bit (MSB) of the addition result, wherein, when the MSB has a first value, the multiplexer treats P bits of the addition result as a division result, and when the MSB has a second value, the multiplexer outputs P logic 1 to serve as the division result, where P is a positive whole number.

摘要翻译： 提供了能够简化总平均灰度的计算的分割单元，图像分析单元和使用该分割单元的显示装置。 分割单元包括：加法器，用于接收第一至第N总线信号以产生相加结果，其中第一至第N总线信号将输入信号移位不同位数，并将逻辑零加到移位位作为补偿， 其中N是正整数，以及多路复用器，用于接收相加结果的最高有效位（MSB），其中当MSB具有第一值时，多路复用器将相加结果的P位视为除法结果，并且 当MSB具有第二值时，多路复用器输出P逻辑1作为除法结果，其中P是正整数。

公开(公告)号：US07346642B1

公开(公告)日：2008-03-18

申请号：US10714554

申请日：2003-11-14

申请人： Willard S. Briggs ,  David W. Matula

发明人： Willard S. Briggs ,  David W. Matula

IPC分类号： G06F7/38

CPC分类号： G06F7/4873 ,  G06F1/0356 ,  G06F7/483 ,  G06F7/535 ,  G06F7/5525 ,  G06F2101/08 ,  G06F2101/12 ,  G06F2207/5356

摘要： Methods for determining the square root, reciprocal square root, or reciprocal of a number performed by a processor of a computer system. The methods produce high precision estimates without using iterative steps. In addition, the methods taught herein utilize compressed tables for the coefficient terms A, B, and C from the quadratic expression Ax2+Bx+C, thus minimizing hardware requirements.

摘要翻译： 用于确定由计算机系统的处理器执行的数字的平方根，倒数平方根或倒数的方法。 该方法在不使用迭代步骤的情况下产生高精度估计。 另外，本文教导的方法利用来自二次表达式Ax 2 + B x + C的系数项A，B和C的压缩表，从而最小化硬件要求。

公开(公告)号：US20050289208A1

公开(公告)日：2005-12-29

申请号：US10874951

申请日：2004-06-23

申请人： John Harrison ,  Ping Tang

发明人： John Harrison ,  Ping Tang

IPC分类号： G06F7/38 ,  G06F7/487

CPC分类号： G06F7/4873 ,  G06F9/30014 ,  G06F2207/5356

摘要： Methods, apparatus, and articles of manufacture for determining quotient values are disclosed. An example method identifies a reciprocal value of a divisor value. A bias value is then identified and a biased quotient value is determined based on a dividend value, the reciprocal value, and at least a portion of the bias value. A quotient value is then determined based on the biased quotient value.

摘要翻译： 公开了用于确定商值的方法，装置和制品。 示例性方法识别除数值的互逆值。 然后识别偏差值，并且基于分红值，互逆值和偏置值的至少一部分来确定偏向商值。 然后基于偏差商数确定商值。

公开(公告)号：US06711603B1

公开(公告)日：2004-03-23

申请号：US09583574

申请日：2000-05-31

申请人： Yasuharu Takenaka

发明人： Yasuharu Takenaka

IPC分类号： G06F752

CPC分类号： G06F7/535 ,  G06F2207/5356

摘要： A fractional arithmetic unit for performing fractional arithmetic operations of different numerators and a common denominator with different precisions as required, the fractional arithmetic unit, including a reciprocal number arithmetic logic unit; and a multiply arithmetic circuit configured to multiply a numerator and a reciprocal number of the denominator as obtained by the reciprocal number arithmetic logic unit. A precision of a calculation performed by the reciprocal number arithmetic logic unit is changed in accordance with a precision as required for each of the fractional arithmetic operations. The multiply arithmetic circuit outputs a result of multiplication as a result of the fractional arithmetic operation, and the results of the fractional arithmetic operations are output with different precisions.

摘要翻译： 分数运算单元，用于根据需要执行不同分数的分数运算和具有不同精度的公分母;分数运算单元，包括倒数算术逻辑单元; 以及乘法运算电路，被配置为乘以由所述倒数算术逻辑单元获得的分母和所述分母的倒数。 由往复数算术逻辑单元执行的计算精度根据每个分数算术运算所需的精度而改变。 乘法运算电路作为分数算术运算的结果输出乘法运算结果，分数运算的结果以不同的精度输出。

公开(公告)号：US5831885A

公开(公告)日：1998-11-03

申请号：US610701

申请日：1996-03-04

申请人： Larry M. Mennemeier

发明人： Larry M. Mennemeier

IPC分类号： G06F7/52 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/3828 ,  G06F2207/5355 ,  G06F2207/5356 ,  G06F7/49936

摘要： A computer implemented method for generating a quotient. The method is exclusive of division operations. The method includes a first step of generating, in response to a first instruction, a first delta by performing an operation between a denominator and a first value. A second step of generating, in response to a second instruction, a second delta by performing an operation between the denominator and the first delta. A third step of generating, in response to the second instruction, a third delta by performing an operation between the second delta and the denominator. A fourth step of joining, in response to a fourth instruction, the third delta to the first delta. Repeating the first through fourth steps until the first delta is equal to a predetermined value. Generating the quotient, in response to a fifth instruction, by performing an operation between the first delta and a numerator.

摘要翻译： 一种用于生成商的计算机实现方法。 该方法不包括除法运算。 该方法包括：通过执行分母和第一值之间的操作，响应于第一指令而产生第一增量的第一步骤。 通过执行分母和第一增量之间的操作，响应于第二指令产生第二增量的第二步骤。 通过执行第二增量和分母之间的操作，响应于第二指令产生第三增量的第三步骤。 第四步骤，响应于第四指令将第三增量加到第一增量。 重复第一到第四步骤，直到第一增量等于预定值。 响应于第五指令，通过执行第一增量和分子之间的操作来生成商。