公开(公告)号：US20130047130A1

公开(公告)日：2013-02-21

申请号：US13209504

申请日：2011-08-15

申请人： Lukas Daellenbach ,  Elmar Gaugler ,  Wilhelm Haller ,  Ralf Richter

发明人： Lukas Daellenbach ,  Elmar Gaugler ,  Wilhelm Haller ,  Ralf Richter

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/82

摘要： A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.

摘要翻译： 计算机化方法，数据处理系统和计算机程序产品减少已经放置和布线的电子电路的缓冲设计的噪声。 对于设计中功率条纹和接地条纹（半间隔）之间的所有区域，形状分为不同的关键级别。 形状根据其临界水平重新排列，使得具有更高临界水平的形状比具有较低临界水平的形状更靠近条纹。

公开(公告)号：US08086657B2

公开(公告)日：2011-12-27

申请号：US12099973

申请日：2008-04-09

申请人： Wilhelm Haller ,  Rolf Sautter ,  Christoph Wandel ,  Ulrich Weiss

发明人： Wilhelm Haller ,  Rolf Sautter ,  Christoph Wandel ,  Ulrich Weiss

IPC分类号： G06F7/50

CPC分类号： H03K19/0941 ,  H03K19/0008

摘要： A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

摘要翻译： 一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到 4位加法器的进位网络中的后级静态和动态逻辑，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。 优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。 优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

公开(公告)号：US07908308B2

公开(公告)日：2011-03-15

申请号：US11748619

申请日：2007-05-15

申请人： Wilhelm Haller ,  Mark Mayo ,  Ricardo H. Nigaglioni ,  Hartmut Sturm

发明人： Wilhelm Haller ,  Mark Mayo ,  Ricardo H. Nigaglioni ,  Hartmut Sturm

IPC分类号： G06F7/508

CPC分类号： G06F7/507

摘要： A Carry-Select Adder structure comprising a carry generation network and a multiplexer to select a particular pre-calculatad sum of a bit-group via orthogonal signal levels of a Hot-Carry signal provided by said carry generation network (21), wherein in order to provide orthogonal signal levels of said Hot-Carry signal, the carry generation network (21) comprises two carry lookahead trees (22, 23) working in parallel to each other, wherein a first carry lookahead tree (22) provides a first signal level of the Hot-Carry signal, and a second carry lookahead tree (23) provides a second, compared to the first signal level inverse signal level of the Hot-Carry signal. Furthermore a method to operate such a Carry-Select Adder is described.

摘要翻译： 一种携带选择加法器结构，包括进位生成网络和多路复用器，用于经由所述进位生成网络（21）提供的热携带信号的正交信号电平来选择位组的特定预计算和，其中按顺序 为了提供所述热携带信号的正交信号电平，进位产生网络（21）包括彼此并行工作的两个进位先行树（22,23），其中第一进位先行树（22）提供第一信号电平 和第二进位先行树（23）提供与热携带信号的第一信号电平反相信号电平相比较的第二进位先行树（23）。 此外，描述了操作这样的进位选择加法器的方法。

公开(公告)号：US20110035711A1

公开(公告)日：2011-02-10

申请号：US12831303

申请日：2010-07-07

申请人： Elmar Gaugler ,  Wilhelm Haller ,  Friedhelm Kessler

发明人： Elmar Gaugler ,  Wilhelm Haller ,  Friedhelm Kessler

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.

摘要翻译： 本发明涉及一种方法和系统，用于根据锁存宏和组合宏重新分配包括多个宏的分层结构的电子电路设计单元的形式化硬件描述。 在第一步骤中，每个宏被解剖成锁存宏和信号锥，每个信号锥包括将宏输入/输出连接到锁存器输出/输入的信号，每个锁存宏包括至少一个锁存器，每个主输入端 所述锁存宏的输出与所述锁存宏中的锁存器的输入或输出一致。 随后，通过沿着单位信号路径合并组合信号锥来创建组合宏。

公开(公告)号：US20080172640A1

公开(公告)日：2008-07-17

申请号：US11622017

申请日：2007-01-11

申请人： Joachim Fenkes ,  Wilhelm Haller ,  Tobias Werner ,  Alexander Woerner

发明人： Joachim Fenkes ,  Wilhelm Haller ,  Tobias Werner ,  Alexander Woerner

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method for comparing two designs of electronic circuits, especially for comparing different versions of a design for an electronic circuit, wherein the design representations comprise several hierarchically related sheets.The method comprises the steps of:a) analyzing the hierarchies of said design versions to identify added, removed and common sheets;b) determining differences between common sheets to identify modified sheets; andc) visualizing the combined hierarchies of said design versions wherein added, removed and modified sheets are marked.

摘要翻译： 一种用于比较电子电路的两个设计的方法，特别是用于比较电子电路的不同版本的设计，其中设计表示包括几个分层相关的片材。 该方法包括以下步骤：a）分析所述设计版本的层次结构，以识别添加，删除和共同的页面; b）确定普通纸张之间的差异以识别修改的纸张; 以及c）可视化所述设计版本的组合层级，其中添加，移除和修改的片材被标记。

公开(公告)号：US07224190B2

公开(公告)日：2007-05-29

申请号：US11009830

申请日：2004-12-10

申请人： Wilhelm Haller ,  Rolf Sautter ,  Monika Strohmer ,  Klaus Thumm

发明人： Wilhelm Haller ,  Rolf Sautter ,  Monika Strohmer ,  Klaus Thumm

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors, and more particularly, to an integrated circuit comprising a dynamic logic function implementing a predetermined logic function with a plurality of transistor stacks, the integrated circuit comprising a precharge node at the input of said logic function implementation, an output latch connected to the output node of said logic function for stabilizing the result of the evaluation of said logic function. The present invention provides such integrated dynamic circuit with a latch, which is protected against instability even in situations involving complex logic functions which are evaluated and their output states are saved by said output latch.

摘要翻译： 本发明涉及硬件逻辑电路领域，特别涉及在计算机处理器中实现的动态硬件逻辑，更具体地，涉及一种集成电路，其包括实现具有多个晶体管堆叠的预定逻辑功能的动态逻辑功能，所述集​​成电路 电路包括在所述逻辑功能实现的输入处的预充电节点，连接到所述逻辑功能的输出节点的输出锁存器，用于稳定所述逻辑功能的评估结果。 本发明提供了具有锁存器的这种集成动态电路，其即使在涉及复杂逻辑功能的情况下也被保护以防止不稳定性，这些功能被评估，并且其输出状态由所述输出锁存器保存。

公开(公告)号：US5928319A

公开(公告)日：1999-07-27

申请号：US969244

申请日：1997-11-13

申请人： Wilhelm Haller ,  Ulrich Krauch ,  Thomas Ludwig ,  Holger Wetter

发明人： Wilhelm Haller ,  Ulrich Krauch ,  Thomas Ludwig ,  Holger Wetter

IPC分类号： G06F7/491 ,  G06F7/50

CPC分类号： G06F7/4912 ,  G06F7/507

摘要： A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.

摘要翻译： 组合的二进制/十进制加法器单元减少了处理二进制编码十进制操作数的操作延迟，并且允许使用组合的二进制/十进制加法单元的处理器单元的增加的周期速率。 对于加法器单元的十进制位数的总和的并行生成和分配，对于每个十进制数位置产生预和。 预计总和预期小数位置的进位，并且在产生了最高十进制位数的进位信号之后需要进行六次校正。 每个十进制位数的进位信号与操作控制信号组合使用，以选择数位位置的正确预置。