公开(公告)号：US06178534B1

公开(公告)日：2001-01-23

申请号：US09076221

申请日：1998-05-11

申请人： Leland Leslie Day ,  Paul Allen Ganfield

发明人： Leland Leslie Day ,  Paul Allen Ganfield

IPC分类号： G01R3128

CPC分类号： G01R31/3016

摘要： A system and method for conducting a repeatable logic test on at least one functional unit of an IC chip includes steps of selecting at least one functional unit of at least several functional units, propagating test data through a part or all functional units of the time domain; and capturing test data of the selected functional unit. The functional units are either selected or held inactive such that only the selected functional unit is allowed to capture the test results for determining a critical timing path within the selected functional unit and only the functional unit. By selecting different combination of the functional unit(s), a number of the critical timing paths are readily determined in the chip.

摘要翻译： 用于对IC芯片的至少一个功能单元进行可重复逻辑测试的系统和方法包括以下步骤：选择至少一个功能单元的至少一个功能单元，通过时域的部分或全部功能单元传播测试数据 ; 并捕获所选功能单元的测试数据。 功能单元被选择或保持不活动，使得仅允许选择的功能单元捕获用于确定所选择的功能单元内的关键定时路径并且仅限于功能单元的测试结果。 通过选择功能单元的不同组合，可以容易地在芯片中确定许多临界定时路径。