公开(公告)号：US06205463B1

公开(公告)日：2001-03-20

申请号：US08850989

申请日：1997-05-05

申请人： Rajesh Manglore ,  Sudarshan Kumar

发明人： Rajesh Manglore ,  Sudarshan Kumar

IPC分类号： G06F750

CPC分类号： G06F7/508

摘要： In one embodiment, an adder is sectioned into a plurality of operational blocks; namely, a first block, second block, and third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section generates a second plurality of sum bits and a first block carry signal. A third block in the second section receives both the section carry signal and the first block carry signal. The third block includes a carry processor which receives the section carry signal and outputs a second block carry signal corresponding to the third block.

摘要翻译： 在一个实施例中，加法器被分割成多个操作块; 即第一块，第二块和第三块。 第一部分中的第一块产生和位和区段进位信号。 第二部分中的第二块产生第二多个和位和第一块进位信号。 第二部分中的第三块接收片段进位信号和第一块进位信号。 第三块包括进位处理器，其接收段进位信号并输出​​对应于第三块的第二块进位信号。

公开(公告)号：US6023767A

公开(公告)日：2000-02-08

申请号：US841839

申请日：1997-05-05

申请人： Sudarshan Kumar ,  James J. C. Lan ,  Rajesh Manglore

发明人： Sudarshan Kumar ,  James J. C. Lan ,  Rajesh Manglore

IPC分类号： G06F1/10 ,  G06F1/04

CPC分类号： G06F1/10

摘要： A method for verifying proper communication between a first circuit and a second circuit of an electronic device. First it is determined which global clocks the first circuit and the second circuit are timed by. Then, the clock signal is shifted between the first and second storage circuits by an amount equal to or greater than a global clock skew budget of the device if it is determined that the first and second storage circuits are timed by different global clocks. Finally, verifying proper operation of the second circuit against a local clock skew budget of the device is done.

摘要翻译： 一种用于验证电子设备的第一电路和第二电路之间的适当通信的方法。 首先确定第一电路和第二电路定时的哪个全局时钟。 然后，如果确定第一和第二存储电路由不同的全局时钟定时，则时钟信号在第一和第二存储电路之间移动等于或大于设备的全局时钟偏差预算的量。 最后，根据设备的本地时钟偏差预算验证第二电路的正确操作。

公开(公告)号：US5661675A

公开(公告)日：1997-08-26

申请号：US414908

申请日：1995-03-31

申请人： Kai J. Chin ,  Sudarshan Kumar

发明人： Kai J. Chin ,  Sudarshan Kumar

IPC分类号： G06F7/50 ,  G06F7/508 ,  H03K19/096 ,  H03K17/80

CPC分类号： G06F7/508 ,  H03K19/0963 ,  G06F2207/3872

摘要： A logic circuit is described. The logic circuit generates a first signal state in response to a first set of input signals, generates a second signal state in response to a second set of input signals, activates a bypass switch in response to the first signal state, and bypasses a domino logic unit in response to the first signal state.

摘要翻译： 描述逻辑电路。 逻辑电路响应于第一组输入信号产生第一信号状态，响应于第二组输入信号产生第二信号状态，响应于第一信号状态激活旁路开关，并绕过多米诺逻辑 响应于第一信号状态的单元。

公开(公告)号：US5136539A

公开(公告)日：1992-08-04

申请号：US285202

申请日：1988-12-16

申请人： Sudarshan Kumar

发明人： Sudarshan Kumar

IPC分类号： G06F7/50 ,  G06F7/506 ,  G06F7/507 ,  G06F7/508

CPC分类号： G06F7/506 ,  G06F7/508

摘要： An metal-oxide-semiconductor (MOS) partitioned carry lookahead adder fabricated from a plurality of four bit slice blocks. Each block provides four sum signals and provides a block carry signal. The blocks are organized into groups of optimum size with logic in each group to generate a group propagate signals. Each block has a block carry line with a single transistor connected between the input and output terminals of the block. The blocks employ an intermediate carry circuit for computing sums in place of full adders. In addition, there is a main carry line with transistors controlled by the group propagate signals. For a 32 bit adder, the maximum pass gate delay in the carry chain is three pass gates.

摘要翻译： 由多个四位片块制造的金属氧化物半导体（MOS）分区进位前瞻加法器。 每个块提供四个和信号并提供块进位信号。 块被组织成最佳尺寸的组，每组中具有逻辑以产生组传播信号。 每个块具有块载入线，其中单个晶体管连接在块的输入和输出端子之间。 块使用中间携带电路来计算总和代替全加器。 此外，还有一个主输送线，晶体管由组传播信号控制。 对于32位加法器，进位链中的最大通过门延迟是三通门。