公开(公告)号：US09553151B2

公开(公告)日：2017-01-24

申请号：US14731744

申请日：2015-06-05

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni ,  Jungwoo Joh

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L27/085

CPC classification number: H01L29/2003 ,  H01L27/085 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.

Abstract translation: 包含GaN FET的半导体器件具有在沟道区域外部的隔离栅极结构，其可操作以阻挡半导体器件的两个区域之间的二维电子气体中的电流。 隔离栅极结构与GaN FET的栅极同时形成，并且具有与栅极相同的结构。

公开(公告)号：US09356117B2

公开(公告)日：2016-05-31

申请号：US14688639

申请日：2015-04-16

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L21/338 ,  H01L29/66 ,  H01L27/02 ,  H01L29/20 ,  H01L29/267 ,  H01L29/778 ,  H01L49/02 ,  H01L29/10 ,  H01L21/8252 ,  H01L27/06 ,  H01L21/8232 ,  H01L29/201 ,  H01L29/205 ,  H01L29/78

CPC classification number: H01L29/7787 ,  H01L21/8232 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/7833

Abstract: A method for forming a semiconductor device including a GaN FET, an overvoltage clamping component, and a voltage dropping component. The GaN FET is formed by forming a low-defect layer comprising gallium nitride, a barrier layer comprising AlxGa1−xN, a gate, and source and drain contacts. The overvoltage clamping component is coupled to a drain node of the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node is less than a safe voltage limit and conducts significant current when the voltage rises above the safe voltage limit. The voltage dropping component is coupled to the overvoltage clamping component and to a terminal for a bias potential. The voltage dropping component provides a voltage drop which increases as current from the overvoltage clamping component increases. The GaN FET turns on when the voltage drop reaches a threshold value.

Abstract translation: 一种用于形成包括GaN FET，过压钳位部件和降压部件的半导体器件的方法。 通过形成包括氮化镓的低缺陷层，包含Al x Ga 1-x N的势垒层，栅极以及源极和漏极接触来形成GaN FET。 过电压钳位部件耦合到GaN FET的漏极节点。 当漏极节点处的电压小于安全电压极限时，过电压钳位元件导通无效电流，并在电压升高到安全电压极限以上时，导通大电流。 降压元件耦合到过电压钳位元件和与偏置电位的端子。 降压元件提供随着过电压钳位元件的电流增加而增加的电压降。 当电压降达到阈值时，GaN FET导通。

公开(公告)号：US09054027B2

公开(公告)日：2015-06-09

申请号：US13886429

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni ,  Jungwoo Joh

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L27/085 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787

Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.

Abstract translation: 包含GaN FET的半导体器件具有在沟道区域外部的隔离栅极结构，其可操作以阻挡半导体器件的两个区域之间的二维电子气体中的电流。 隔离栅极结构与GaN FET的栅极同时形成，并且具有与栅极相同的结构。