公开(公告)号：US20060133138A1

公开(公告)日：2006-06-22

申请号：US11316141

申请日：2005-12-21

Applicant: Jian Chen ,  Chi-Ming Wang

Inventor： Jian Chen ,  Chi-Ming Wang

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

Abstract: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations. A second program voltage step size that is larger than a nominal step size is used in one embodiment when programming select memory cells or word lines, such as the last word line to be programmed for a NAND string.

Abstract translation: 根据各种实施例的系统和方法可以提供非易失性半导体存储器中减少的程序干扰。 在一个实施例中，使用与编程其他单元或字线的相应级别不同的一个或多个程序验证电平或电压对连接到NAND串的最后字线的选择存储器单元进行编程。 一个示例性实施例包括在编程在程序操作期间编程用于字符串的最后一个字线时，使用较低的阈值电压验证电平来选择物理状态。 另一个实施例包括将较低编程电压施加到最后字线的编程存储单元以选择物理状态。 在一些示例性实施方式中，建立读取使用较低验证电平编程的状态的附加读取电平。 在一个实施例中，当编程选择存储器单元或字线（诸如要为NAND串编程的最后字线）时，使用大于标称步长的第二编程电压步长。

公开(公告)号：US20060098483A1

公开(公告)日：2006-05-11

申请号：US11315817

申请日：2005-12-21

Applicant: Jian Chen ,  Chi-Ming Wang

Inventor： Jian Chen ,  Chi-Ming Wang

IPC: G11C16/04

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

Abstract: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations. A second program voltage step size that is larger than a nominal step size is used in one embodiment when programming select memory cells or word lines, such as the last word line to be programmed for a NAND string.

公开(公告)号：US07020017B2

公开(公告)日：2006-03-28

申请号：US10818597

申请日：2004-04-06

Applicant: Jian Chen ,  Chi-Ming Wang

Inventor： Jian Chen ,  Chi-Ming Wang

IPC: G11C16/04

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

Abstract: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations. A second program voltage step size that is larger than a nominal step size is used in one embodiment when programming select memory cells or word lines, such as the last word line to be programmed for a NAND string.

Abstract translation: 根据各种实施例的系统和方法可以提供非易失性半导体存储器中减少的程序干扰。 在一个实施例中，使用与编程其他单元或字线的相应级别不同的一个或多个程序验证电平或电压对连接到NAND串的最后字线的选择存储器单元进行编程。 一个示例性实施例包括在编程在程序操作期间编程用于字符串的最后一个字线时，使用较低的阈值电压验证电平来选择物理状态。 另一个实施例包括将较低编程电压施加到最后字线的编程存储单元以选择物理状态。 在一些示例性实施方式中，建立读取使用较低验证电平编程的状态的附加读取电平。 在一个实施例中，当编程选择存储器单元或字线（诸如要为NAND串编程的最后字线）时，使用大于标称步长的第二编程电压步长。

公开(公告)号：US20060023507A1

公开(公告)日：2006-02-02

申请号：US11238911

申请日：2005-09-28

Applicant: John Mangan ,  Daniel Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker Quader

Inventor： John Mangan ,  Daniel Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker Quader

IPC: G11C7/10 ,  G11C11/34

CPC classification number: G11C7/12 ,  G11C16/12 ,  G11C16/3427 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1204

Abstract: In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.