公开(公告)号：US12125528B2

公开(公告)日：2024-10-22

申请号：US17896929

申请日：2022-08-26

申请人： KIOXIA CORPORATION

发明人： Naofumi Abiko

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

摘要： A semiconductor memory device includes memory cell transistors and a control circuit. In a write operation, the control circuit executes multiple loops each including a program operation, a verify operation, and a bit scan operation. In the bit scan operation, the control circuit performs, a first process of generating verify result data in parallel for a group of memory cell transistors having different target threshold voltage states, the verify result data for each memory cell transistor in the group indicating whether the memory cell transistor has reached its target threshold voltage state, and a second process of calculating for each of the target threshold voltage states, the number of memory cell transistors that have not reached their target threshold voltage states.

公开(公告)号：US20240321348A1

公开(公告)日：2024-09-26

申请号：US18675257

申请日：2024-05-28

申请人： KIOXIA CORPORATION

发明人： Naomi TAKEDA ,  Masanobu SHIRAKAWA ,  Akio SUGAHARA

IPC分类号： G11C11/56 ,  G06F12/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G06F12/0246

摘要： According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

公开(公告)号：US20240312533A1

公开(公告)日：2024-09-19

申请号：US18677727

申请日：2024-05-29

申请人： Kioxia Corporation

发明人： Yoshihisa KOJIMA

IPC分类号： G11C16/32 ,  G11C7/04 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C16/32 ,  G11C7/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3495 ,  G11C2211/5648

摘要： A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.

公开(公告)号：US20240282389A1

公开(公告)日：2024-08-22

申请号：US18654302

申请日：2024-05-03

申请人： Kioxia Corporation

发明人： Hiroyuki NAGASHIMA

IPC分类号： G11C16/26 ,  G06F11/10 ,  G06F11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34

CPC分类号： G11C16/26 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/3418 ,  G06F11/3466 ,  G06F2201/88 ,  G11C16/0483

摘要： According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.

公开(公告)号：US20240265980A1

公开(公告)日：2024-08-08

申请号：US18359904

申请日：2023-07-27

申请人： SK hynix Inc.

发明人： Yeong Jo MUN ,  Dong Hun KWAK ,  Se Chun PARK

IPC分类号： G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459

摘要： A memory device includes: a memory block including a plurality of memory cells; a peripheral circuit for performing a program operation on selected memory cells among the plurality of memory cells; and a control logic for controlling the program operation of the peripheral circuit. The control logic controls the peripheral circuit to perform a foggy program operation on first memory cells connected to a first word line among the plurality of memory cells, perform a foggy program operation on second memory cells connected to a second word line adjacent to the first word line among the plurality of memory cells, and perform a fine program operation on the first memory cells, based on a target program state of the second memory cells.

公开(公告)号：US12046267B2

公开(公告)日：2024-07-23

申请号：US17895803

申请日：2022-08-25

申请人： SanDisk Technologies LLC

发明人： Kazuki Yamauchi

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/10

摘要： A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to program and verify the memory cells during a program operation. The memory cells associated with predetermined ones of the data states are not verified until the memory cells associated with specific prior ones of the data states finish programming to define verify windows ranging between each one of the specific prior ones of the data states and each one of the predetermined ones. The control means adjusts the verify windows in response to the memory cells associated with one of the specific prior ones of the data states not finishing programming before the one of the predetermined ones of the at least one of the verify windows is verified.

公开(公告)号：US12040022B2

公开(公告)日：2024-07-16

申请号：US17535220

申请日：2021-11-24

申请人： SK hynix Inc.

发明人： Hee Youl Lee

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/3459

摘要： A method of operating a semiconductor memory device includes performing a plurality of program loops for programming selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes a program phase and a verify phase. The program phase includes setting a state of a select line connected to a selected memory block including the selected memory cells, wherein setting the state of the select line connected to the selected memory block comprises applying a voltage to the select line based on a program progress state of the selected memory cells, setting a state of a bit line connected to the selected memory block, applying a program voltage to a selected word line among word lines connected to the selected memory block and applying a pass voltage to an unselected word line.

公开(公告)号：US12033693B2

公开(公告)日：2024-07-09

申请号：US18451182

申请日：2023-08-17

申请人： KIOXIA CORPORATION

发明人： Naomi Takeda ,  Masanobu Shirakawa ,  Akio Sugahara

IPC分类号： G11C16/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G06F12/02

CPC分类号： G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G06F12/0246

摘要： According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

公开(公告)号：US20240194243A1

公开(公告)日：2024-06-13

申请号：US18581018

申请日：2024-02-19

申请人： Samsung Electronics Co., Ltd.

发明人： Hee-Woong KANG ,  Dong-Hun KWAK ,  Jun-Ho SEO ,  Hee-Won LEE

IPC分类号： G11C11/4074 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

CPC分类号： G11C11/4074 ,  G11C7/109 ,  G11C7/12 ,  G11C8/12 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3436 ,  G11C2207/2209

摘要： A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US20240170058A1

公开(公告)日：2024-05-23

申请号：US18522111

申请日：2023-11-28

申请人： PURE STORAGE, INC.

发明人： HARI KANNAN ,  PETER E. KIRKPATRICK

IPC分类号： G11C11/56 ,  G06F3/06 ,  G06F12/02 ,  G11C16/10

CPC分类号： G11C11/5628 ,  G06F3/061 ,  G06F3/0614 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0246 ,  G11C16/10 ,  G11C16/102 ,  G06F2212/7203

摘要： A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.