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    RECONFIGURABLE PROCESSOR AND OPERATING METHOD OF THE SAME
    42.
    发明申请
    RECONFIGURABLE PROCESSOR AND OPERATING METHOD OF THE SAME 有权
    可重构加工器及其操作方法

    公开(公告)号：US20100174885A1

    公开(公告)日：2010-07-08

    申请号：US12563350

    申请日：2009-09-21

    Applicant: Il-hyun PARK ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  Yeon-gon Cho ,  Bernhard Egger ,  Woon Seo

    Inventor： Il-hyun PARK ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  Yeon-gon Cho ,  Bernhard Egger ,  Woon Seo

    IPC: G06F15/76 ,  G06F9/00

    CPC classification number: G06F15/7867 ,  G06F9/30072 ,  Y02D10/12 ,  Y02D10/13

    Abstract: Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory including configuration information about an operation of a function unit, and a distributed routing configuration memory including configuration information about routing. The distributed operation configuration memory may be activated according to a predicate signal.

    Abstract translation: 提供了一种可重构处理器及其操作方法。 可重构处理器可以使用分配给每个操作单元的配置存储器。 分布式配置存储器可以被分成包括关于功能单元的操作的配置信息的分布式操作配置存储器，以及包括关于路由的配置信息的分布式路由配置存储器。 可以根据谓词信号激活分布式操作配置存储器。

    Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array
    43.
    发明授权
    Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array 有权
    在可重构粗粒度阵列中循环处理中的中断处理方法和装置

    公开(公告)号：US07529917B2

    公开(公告)日：2009-05-05

    申请号：US11519858

    申请日：2006-09-13

    Applicant: Soo Jung Ryu ,  Jeong Wook Kim ,  Dong-Hoon Yoo ,  Hee Seok Kim

    Inventor： Soo Jung Ryu ,  Jeong Wook Kim ,  Dong-Hoon Yoo ,  Hee Seok Kim

    IPC: G06F9/00

    CPC classification number: G06F9/4812

    Abstract: A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while executing the sub-loop in the coarse grained array, the interrupt request is processed after the executing of the sub-loop is completed.

    Abstract translation: 一种包括包括多个功能单元和多个寄存器文件的粗粒度阵列的处理器，其中由粗粒度阵列执行的循环被分割成多个子循环，并且当执行中断请求时发生中断请求 在粗粒子数组中的子循环，中断请求在子循环执行完成后被处理。

    MEMORY ACCESS METHOD USING THREE DIMENSIONAL ADDRESS MAPPING
    44.
    发明申请
    MEMORY ACCESS METHOD USING THREE DIMENSIONAL ADDRESS MAPPING 有权
    使用三维地址映射的存储器访问方法

    公开(公告)号：US20080209159A1

    公开(公告)日：2008-08-28

    申请号：US11828440

    申请日：2007-07-26

    Applicant: Jong Myon KIM ,  Soojung RYU ,  Dong-Hoon YOO ,  Hong-Seok KIM ,  Hee Seok KIM ,  Jeongwook KIM ,  Kyoung June MIN

    Inventor： Jong Myon KIM ,  Soojung RYU ,  Dong-Hoon YOO ,  Hong-Seok KIM ,  Hee Seok KIM ,  Jeongwook KIM ,  Kyoung June MIN

    IPC: G06F12/00

    CPC classification number: G06F8/443 ,  G06F8/447 ,  G06F12/0207

    Abstract: A memory access method includes: obtaining a, b, and c from a program code for accessing a memory with a triple loop in a program, a being a number of values which an inner-most loop variable of the triple loop may have, b being a number of values which a middle loop variable of the triple loop may have, and c being a number of values which an outer-most loop variable of the triple loop may have; obtaining a starting address of the memory accessed by the triple loop; and obtaining an a×b×c number of addresses of the memory accessed by the triple loop using the starting address and a function.

    Abstract translation: 存储器访问方法包括：从程序中用于访问具有三重循环的存储器的程序代码获取a，b和c，所述三循环的最内循环变量可以具有多个值，b 是三重循环的中间循环变量可能具有的多个值，c是三重循环的最外圈循环变量可能具有的值的数量; 获取由三重循环访问的存储器的起始地址; 并且使用起始地址和功能获得由三重回路访问的存储器的axbxc个地址数。

    Apparatus and method of exception handling for reconfigurable architecture
    48.
    发明授权
    Apparatus and method of exception handling for reconfigurable architecture 有权
    可重构架构异常处理的装置和方法

    公开(公告)号：US09152418B2

    公开(公告)日：2015-10-06

    申请号：US11487407

    申请日：2006-07-17

    Applicant: Hee Seok Kim ,  Dong-Hoon Yoo ,  Jeong Wook Kim ,  Soo Jung Ryu

    Inventor： Hee Seok Kim ,  Dong-Hoon Yoo ,  Jeong Wook Kim ,  Soo Jung Ryu

    IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/3012 ,  G06F9/30105 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3863

    Abstract: A processor including a coarse grained array including a plurality of processing elements, a central register file including a first plurality of register files, a shadow central register file including a second plurality of register files, each of the second plurality of register files corresponding to each of the first plurality of register files included in the central register file, and a plurality of shadow register files, each of the plurality of shadow register files corresponding to each of a third plurality of register files included in predetermined processing elements selected from the plurality of processing elements.

    Abstract translation: 一种处理器，包括包括多个处理元件的粗粒子阵列，包括第一多个寄存器文件的中央寄存器文件，包括第二多个寄存器文件的影子中心寄存器文件，与每个寄存器文件相对应的第二多个寄存器堆中的每一个 包括在中央寄存器文件中的第一多个寄存器文件和多个影子寄存器文件，多个影子寄存器文件中的每一个对应于包括在从多个寄存器文件中选择的预定处理元件中的第三多个寄存器文件中的每一个 处理元件。

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