公开(公告)号：US6013579A

公开(公告)日：2000-01-11

申请号：US176385

申请日：1998-10-21

Applicant: Kun-Chih Wang ,  Tri-Rung Yew

Inventor： Kun-Chih Wang ,  Tri-Rung Yew

IPC: H01L21/768 ,  H01L21/00

CPC classification number: H01L21/76829 ,  H01L21/76802 ,  H01L21/76897

Abstract: A self-aligned via process to prevent the via poisoning includes forming a hydrogen silsesquioxane layer on the substrate and over a pre-formed metal layer, forming an etching stop layer on the hydrogen silsesquioxane layer, forming an oxide layer on the etching stop layer, and then proceeding with a two-step etching process to form a via. The two-step etching process first patterns the oxide layer using a patterned photoresist layer as a mask, and then patterns the etching stop layer together with the hydrogen silsesquioxane layer using the patterned oxide layer as a mask. Because the etching stop layer prevents the hydrogen silsesquioxane layer from reacting with the oxygen plasma during the photoresist layer removal process, via poisoning is eliminated.

Abstract translation: 用于防止通路中毒的自对准通孔工艺包括在基板上和预成型的金属层上形成氢倍半硅氧烷层，在氢倍半硅氧烷层上形成蚀刻停止层，在蚀刻停止层上形成氧化物层， 然后进行两步蚀刻工艺以形成通孔。 两步蚀刻工艺首先使用图案化的光致抗蚀剂层作为掩模对氧化物层进行图案化，然后使用图案化氧化物层作为掩模，将蚀刻停止层与氢倍半硅氧烷层一起图案化。 因为蚀刻停止层防止在光致抗蚀剂层去除过程中氢倍半硅氧烷层与氧等离子体反应，消除了中毒。

公开(公告)号：US5976984A

公开(公告)日：1999-11-02

申请号：US1416

申请日：1997-12-30

Applicant: Coming Chen ,  Chih-Chien Liu ,  Kun-Chih Wang ,  Tri-Rung Yew

Inventor： Coming Chen ,  Chih-Chien Liu ,  Kun-Chih Wang ,  Tri-Rung Yew

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76829 ,  H01L2924/0002

Abstract: A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface of the interconnects. An etch-stopping layer is then formed on top of the first dielectric layer, followed by the formation of a second dielectric layer on top of the etch-stopping layer. A photoresist layer then covers the second dielectric layer and reveals the surface regions of the second dielectric layer designated for the formation of the vias. A main etching procedure is then performed to etch into the second dielectric layer down to the surface of the etch-stopping layer, thereby forming the first section of the vias. An over-etching procedure is then implemented to strip off the etch-stopping layer and further etches into the first dielectric layer and the etching is then stopped when the surface of the interconnects are revealed to conclude the formation of the vias.

Abstract translation: 公开了一种在半导体IC器件中形成通孔的方法，该半导体IC器件具有与互连表面的充分接触并且没有不足够的着陆。 该方法具有形成在IC器件的衬底上的金属层中的互连，并且覆盖互连表面的第一介电层被形成。 然后在第一介电层的顶部上形成蚀刻停止层，随后在蚀刻停止层的顶部形成第二电介质层。 光致抗蚀剂层然后覆盖第二电介质层并且显露指定用于形成通孔的第二电介质层的表面区域。 然后执行主蚀刻程序以蚀刻到第二介电层中，直到蚀刻停止层的表面，从而形成通孔的第一部分。 然后实施过蚀刻程序以剥离蚀刻停止层并进一步蚀刻到第一介电层中，然后当显露互连表面以终止形成通孔时，停止蚀刻。