公开(公告)号：US20240363402A1

公开(公告)日：2024-10-31

申请号：US18769054

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66

CPC分类号： H01L21/76843 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L29/66795

摘要： An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

公开(公告)号：US20240363401A1

公开(公告)日：2024-10-31

申请号：US18201200

申请日：2023-05-24

申请人： Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Janbo Zhang ,  Li-Wei Feng

IPC分类号： H01L21/768 ,  H01L23/528

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528

摘要： A contact pad structure and a manufacturing method thereof are disclosed in the present invention. The contact pad structure includes a substrate, a first dielectric layer, a second dielectric layer, first contact pads, an etching stop layer, a first void, and a second void. The first contact pads are disposed on a first region of the substrate. The first dielectric layer is disposed on the substrate, covers the first contact pads, and includes a recess located between two adjacent first contact pads. The etching stop layer is disposed on the first dielectric layer and partially located in the recess. The second dielectric layer is disposed on the etching stop layer and partially located in the recess. The first void is disposed in the etching stop layer and located in the recess. The second void is disposed in the second dielectric layer and located in the recess.

公开(公告)号：US20240363399A1

公开(公告)日：2024-10-31

申请号：US18771016

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Ju Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Meng-Han Chou

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC分类号： H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/785

摘要： A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

公开(公告)号：US12131946B2

公开(公告)日：2024-10-29

申请号：US17584210

申请日：2022-01-25

申请人： SiEn (QingDao) Integrated Circuits Co., Ltd.

发明人： Min-Hwa Chi ,  Zhaosheng Meng ,  Xian Zhang

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L29/40

CPC分类号： H01L21/76877 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76829 ,  H01L29/401

摘要： The present invention relates to a method of forming contact holes of a CMOS device and a method of making a CMOS device. Because a carbon cap layer or a carbon rich layer is formed on a etching stop layer, when etching reaches the etching stop layer with less depth, great polymer protecting the etching stop layer from etching will be formed in the etching stop layer. As such, when etching reaches the contact holes with more depth, the contact holes with less depth may be protected from over-etching until etching the contact holes with more depth is finished. Over-etching may be avoided, and meanwhile the contact holes with more depth may be fully etched to avoid from under-etching.

公开(公告)号：US20240355730A1

公开(公告)日：2024-10-24

申请号：US18761397

申请日：2024-07-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jia-En Lee ,  Po-Yu Huang ,  Shih-Che Lin ,  Chao-Hsun Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Feng-Yu Chang

IPC分类号： H01L23/522 ,  H01L21/3115 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5228 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L28/24

摘要： Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity β-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity β-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity β-W phase. The β-W converts to a low-resistivity α-phase of tungsten in the regions not pre-treated with impurities.

公开(公告)号：US20240355685A1

公开(公告)日：2024-10-24

申请号：US18650718

申请日：2024-04-30

申请人： Micron Technology, Inc.

发明人： Amitava Majumdar ,  Radhakrishna Kotti ,  Mallesh Rajashekharaiah

IPC分类号： H01L21/66 ,  G11C13/00 ,  H01J37/04 ,  H01J37/28 ,  H01L21/768 ,  H01L23/528 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H01L22/12 ,  H01J37/28 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5283 ,  H10B63/84 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  H01J37/04 ,  H01J2237/2804 ,  H01J2237/2814 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8825

摘要： Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.

公开(公告)号：US20240339355A1

公开(公告)日：2024-10-10

申请号：US18743574

申请日：2024-06-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Yu LIN ,  Zhiqiang WU ,  Chung-Wei WU ,  Chun-Fu CHENG

IPC分类号： H01L21/768 ,  H01L21/02

CPC分类号： H01L21/76802 ,  H01L21/0217 ,  H01L21/02362 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76897

摘要： The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

公开(公告)号：US20240332399A1

公开(公告)日：2024-10-03

申请号：US18732393

申请日：2024-06-03

申请人： Intel Corporation

发明人： Tahir GHANI ,  Byron HO ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US20240332068A1

公开(公告)日：2024-10-03

申请号：US18738256

申请日：2024-06-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Jen Lo ,  Po-Cheng Shih ,  Syun-Ming Jang ,  Tze-Liang Lee

IPC分类号： H01L21/768 ,  G03F7/038 ,  G03F7/039 ,  G03F7/20 ,  H01L21/027

CPC分类号： H01L21/76823 ,  G03F7/038 ,  G03F7/039 ,  G03F7/2004 ,  G03F7/2022 ,  H01L21/0274 ,  H01L21/76802 ,  H01L21/76877

摘要： A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

公开(公告)号：US12107003B2

公开(公告)日：2024-10-01

申请号：US18303839

申请日：2023-04-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Te-Chih Hsiung ,  Yi-Chun Chang ,  Jyun-De Wu ,  Yi-Chen Wang ,  Yuan-Tien Tu ,  Huan-Just Lin

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311

CPC分类号： H01L21/76826 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53295 ,  H01L21/31116 ,  H01L21/76877

摘要： A semiconductor device includes a gate structure, source/drain regions, source/drain contacts, a gate dielectric cap, an etch stop layer, and a gate contact. The gate structure is over a substrate. The source/drain regions are at opposite sides of the gate structure. The source/drain contacts are over the source/drain regions, respectively. The gate dielectric cap is over the gate structure and has opposite sidewalls interfacing the source/drain contacts.