公开(公告)号：US11755062B2

公开(公告)日：2023-09-12

申请号：US17933680

申请日：2022-09-20

Applicant: STMicroelectronics Application GMBH

Inventor： Rolf Nandlinger

IPC: G06F1/14

CPC classification number: G06F1/14

Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.

公开(公告)号：US20220357973A1

公开(公告)日：2022-11-10

申请号：US17736590

申请日：2022-05-04

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMicroelectronics International N.V.

Inventor： Boris VITTORELLI ,  Simrata BATRA ,  Vivek Kumar SOOD ,  Deepak BARANWAL

IPC: G06F9/455

Abstract: A communication system couples a plurality of processing cores together, each having an associated register storing a virtual machine ID, which is inserted into requests sent by the respective processing core. A master circuit has associated a master interface circuit, wherein the master interface circuit has associated register for storing a second virtual machine ID, which is inserted into requests sent by the master circuit. A slave circuit has associated a slave interface circuit configured to selectively forward read or write requests addressed to an address sub-range. The slave interface circuit has associated a third register storing a third virtual machine ID associated with the address sub-range and is configured to receive a request addressed to the address sub-range, extract from the request a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID, and then either forwards or rejects the request.

公开(公告)号：US11483909B2

公开(公告)日：2022-10-25

申请号：US17523641

申请日：2021-11-10

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application S.R.O.

Inventor： Donato Tagliavia ,  Vincenzo Polisi ,  Calogero Andrea Trecarichi ,  Francesco Nino Mammoliti ,  Jochen Barthel ,  Ludek Beran

IPC: H05B45/10 ,  H05B45/38 ,  H05B45/46 ,  H05B45/375

Abstract: A control circuit for a voltage source generates a reference signal for a voltage source, wherein the reference signal indicates a requested output voltage to be generated by the voltage source. A digital feed-forward control circuit computes a digital feed-forward regulation value indicative of a requested output voltage by determining a maximum voltage drop at strings of solid-state light sources. A digital feed-back control circuit determines a minimum voltage drop for current regulators/limiters for the strings and determines a digital feed-back correction value as a function of the minimum voltage drop. The control circuit then sets the reference signal after a start-up as a function of the digital feed-forward regulation value and corrects the reference signal as a function of the digital feed-back correction value.

公开(公告)号：US11480994B2

公开(公告)日：2022-10-25

申请号：US16857544

申请日：2020-04-24

Applicant: STMicroelectronics Application GmbH

Inventor： Rolf Nandlinger

IPC: G06F1/14

Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.

公开(公告)号：US20220214430A1

公开(公告)日：2022-07-07

申请号：US17568317

申请日：2022-01-04

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics Application GmbH

Inventor： Romeo LETOR ,  Roberto TIZIANI ,  Alfio RUSSO ,  Antoine PAVLIN ,  Nadia LECCI ,  Manuel GAERTNER

IPC: G01S7/484 ,  G01S7/481

Abstract: An electronic module for generating light pulses includes an electronic card or interposer, a LASER-diode lighting module, and a LASER-diode driver module. The interposer has an edge recess in which the lighting module is completely inserted. The driver module is arranged on top of the interposer and the lighting module. The electrical connections for driving the LASER diodes are obtained without resorting to wire bonding in order to reduce the parasitic inductances.

公开(公告)号：US20210382779A1

公开(公告)日：2021-12-09

申请号：US17406910

申请日：2021-08-19

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F11/07 ,  G06F11/10

Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.

公开(公告)号：US11113136B2

公开(公告)日：2021-09-07

申请号：US16289405

申请日：2019-02-28

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10

Abstract: A processing system includes a plurality of circuits configured to generate a plurality of error signals. The processing system further includes a plurality of error pads and a fault collection circuit configured to receive the plurality of error signals and to generate a respective combined error signal for each of the plurality of error pads. The fault collection circuit includes a combinational logic circuit configured to generate the combined error signal by selectively routing the plurality of error signals to the plurality of error pads as a function of a set of configuring bits.

公开(公告)号：US10922015B2

公开(公告)日：2021-02-16

申请号：US16002534

申请日：2018-06-07

Applicant: STMicroelectronics Application GMBH

Inventor： Roberto Colombo

IPC: G06F3/06 ,  G06F15/78 ,  G06F15/177

Abstract: A processing system includes a processing unit; a non-volatile memory storing configuration data; and a configuration data client including a register, wherein the configuration data client is configured to receive the configuration data and store the configuration data in the register. The processing system further includes a hardware configuration circuit configured to read the configuration data from the non-volatile memory and transmit the configuration data, read from the non-volatile memory, to the configuration data client. The hardware configuration circuit may be configured to receive a command, including an access request, from the processing unit and selectively execute the access request.

公开(公告)号：US20210004339A1

公开(公告)日：2021-01-07

申请号：US16933752

申请日：2020-07-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Nirav Prashantkumar Trivedi ,  Sandip Atal ,  Rolf Nandlinger

IPC: G06F13/28 ,  H03M1/38 ,  H03M1/12

Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.

公开(公告)号：US10855529B2

公开(公告)日：2020-12-01

申请号：US16679796

申请日：2019-11-11

Applicant: STMicroelectronics Application GmbH

Inventor： Roberto Colombo

IPC: H04L12/24 ,  H03K19/1776 ,  H04L29/06 ,  H04L29/08

Abstract: A hardware configuration circuit can sequentially read data packets from a non-volatile memory. For a first data packet, the circuit is configured to store the configuration data and the address included in the data packet in the register, select a target configuration data client circuit as a function of the address included in the first data packet, transmit a first data signal that includes the configuration data included in the first data packet to the target configuration data client circuit, receive a second data signal that includes configuration data stored in the target configuration data client circuit and the address associated with the target configuration data client circuit, and compare the configuration data and address received from the target configuration data client circuit with the configuration data and address stored in the register.