公开(公告)号：US5781480A

公开(公告)日：1998-07-14

申请号：US902009

申请日：1997-07-29

Applicant: Scott George Nogle ,  Alan S. Roth ,  Shuang Li Ho

Inventor： Scott George Nogle ,  Alan S. Roth ,  Shuang Li Ho

IPC: G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/16 ,  G11C11/41 ,  G11C16/04

CPC classification number: G11C8/16 ,  G11C7/1072 ,  G11C7/1075 ,  G11C7/22

Abstract: A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells, where each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) compares addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

Abstract translation: 流水线双端口集成电路存储器（20）包括静态随机存取存储器（SRAM）单元的阵列（30），其中每个存储器单元（80）连接到单个字线（72）和单个位 线对（74,76）。 控制电路（32）控制对存储器单元的访问，其中基本同时的访问请求在正在访问存储器（20）的数据处理器的时钟信号的单个周期内被顺序地服务。 地址冲突检测器（110）比较提供给两个端口的地址，并且产生用于确定两个端口中的哪一个被首先服务的匹配信号，独立于从哪个端口读取或写入。 由于使用单端口SRAM阵列（30）获得双端口功能，所以可以使用相对较少的集成电路表面积制造存储器（20），因此以较低的成本。