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公开(公告)号:US09786557B1
公开(公告)日:2017-10-10
申请号:US15096818
申请日:2016-04-12
Inventor: Cheng Chi , Ruilong Xie
IPC: H01L21/4763 , H01L21/768 , H01L21/8234 , H01L29/45 , H01L29/417 , H01L27/088 , H01L23/528 , H01L23/522 , H01L23/532 , H01L29/06
CPC classification number: H01L21/76897 , H01L21/76802 , H01L21/76877 , H01L21/823475 , H01L23/5226 , H01L23/53209 , H01L23/53228 , H01L23/53257 , H01L27/0886 , H01L29/0649 , H01L29/41766 , H01L29/45
Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.
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42.
公开(公告)号:US20170092721A1
公开(公告)日:2017-03-30
申请号:US15363607
申请日:2016-11-29
Inventor: Cheng Chi , Fee Li Lie , Chi-Chun Liu , Ruilong Xie
IPC: H01L29/06 , H01L27/088
Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.
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