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公开(公告)号：US20140093069A1
公开(公告)日：2014-04-03
申请号：US13631165
申请日：2012-09-28
IPC分类号： H04L9/28
CPC分类号： G09C1/00 , G06F9/30007 , H04L9/0643 , H04L2209/125
摘要： A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs.
摘要翻译： 处理器包括第一执行单元，用于接收和执行第一指令以处理安全散列算法256（SHA256）消息调度操作的第一部分，所述第一指令具有与第一存储位置相关联的第一操作数，以存储第一组 消息输入和与第二存储位置相关联的第二操作数，以存储第二组消息输入。 所述处理器还包括第二执行单元，用于接收和执行用于处理所述SHA256消息调度操作的第二部分的第二指令，所述第二指令具有与第三存储位置相关联的第三操作数，以存储所述第一部分的中间结果;以及 第三组消息输入和与第四存储位置相关联的第四操作数，以存储第四组消息输入。
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42.发明申请公开(公告)号：US20140093068A1
公开(公告)日：2014-04-03
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译： 根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联 具有存储多个偶数字的第二存储位置和第三操作数。 处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮 由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。
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公开(公告)号：US20170091120A1
公开(公告)日：2017-03-30
申请号：US14865675
申请日：2015-09-25
申请人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
CPC分类号： G06F12/1408 , G06F11/1608 , G06F11/327 , G06F13/00 , G06F21/575 , G06F21/79 , G06F2212/1052
摘要： A host central processing unit subsystem that writes information to external memory may provide policy to the external memory. Then every time a write comes from the host subsystem, a memory controller within the memory may check the write against the policy stored in the memory and decide whether or not to implement the write.
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公开(公告)号：US08874933B2
公开(公告)日：2014-10-28
申请号：US13631150
申请日：2012-09-28
IPC分类号： G06F21/22
CPC分类号： G06F21/72 , G06F9/30007 , G06F9/30036 , H04L9/0643
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a SHA1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four SHA states, the second operand specifying a second storage location storing a plurality of SHA1 message inputs in combination with a fifth SHA1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the SHA1 round operations on the SHA1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand.
摘要翻译： 根据一个实施例，处理器包括指令解码器，用于接收处理SHA1散列算法的第一指令，所述第一指令具有第一操作数，第二操作数和第三操作数，所述第一操作数指定存储四个 SHA指出，第二操作数指定存储与第五SHA1状态相结合的多个SHA1消息输入的第二存储位置。 所述处理器还包括执行单元，其响应于所述第一指令而耦合到所述指令解码器，以使用所述第一和第二操作数获得的所述SHA1状态和从所述第一和第二操作数获得的所述消息输入执行至少四轮所述SHA1循环操作， 逻辑功能在第三个操作数中指定。
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公开(公告)号：US08838997B2
公开(公告)日：2014-09-16
申请号：US13631165
申请日：2012-09-28
IPC分类号： H04L9/28
CPC分类号： G09C1/00 , G06F9/30007 , H04L9/0643 , H04L2209/125
摘要： A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs.
摘要翻译： 处理器包括第一执行单元，用于接收和执行第一指令以处理安全散列算法256（SHA256）消息调度操作的第一部分，所述第一指令具有与第一存储位置相关联的第一操作数，以存储第一组 消息输入和与第二存储位置相关联的第二操作数，以存储第二组消息输入。 所述处理器还包括第二执行单元，用于接收和执行用于处理所述SHA256消息调度操作的第二部分的第二指令，所述第二指令具有与第三存储位置相关联的第三操作数，以存储所述第一部分的中间结果;以及 第三组消息输入和与第四存储位置相关联的第四操作数，以存储第四组消息输入。
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46.发明申请INSTRUCTION AND LOGIC TO PROVIDE SIMD SECURE HASHING ROUND SLICE FUNCTIONALITY 有权指示和逻辑提供SIMD安全冲击圆形功能公开(公告)号：US20140189368A1
公开(公告)日：2014-07-03
申请号：US13731004
申请日：2012-12-29
申请人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap
发明人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap
IPC分类号： G06F21/60
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G06F15/8007 , G06F21/602 , G06F21/64
摘要： Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.
摘要翻译： 说明和逻辑提供SIMD安全散列圆切片功能。 一些实施例包括处理器，包括：解码级，用于解码用于SIMD安全散列算法圆切片的指令，指定源数据操作数集合的指令，消息加常数操作数集合，安全散列的圆切片部分 圆周运算，旋转设定部分旋转设定。 处理器执行单元响应于解码的指令，在源数据操作数集合上执行循环迭代的安全散列圆切片集合，应用消息加常数操作数集合和旋转器集合，并且存储 SIMD目的寄存器中的指令。 该指令的一个实施例将哈希循环类型指定为四个MD5循环类型之一。 其他实施例可以通过立即操作数来指定散列循环类型，作为三种SHA-1轮型之一或SHA-2轮型。
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公开(公告)号：US20140095891A1
公开(公告)日：2014-04-03
申请号：US13631150
申请日：2012-09-28
IPC分类号： G06F21/22
CPC分类号： G06F21/72 , G06F9/30007 , G06F9/30036 , H04L9/0643
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a SHA1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four SHA states, the second operand specifying a second storage location storing a plurality of SHA1 message inputs in combination with a fifth SHA1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the SHA1 round operations on the SHA1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand.
摘要翻译： 根据一个实施例，处理器包括指令解码器，用于接收处理SHA1散列算法的第一指令，所述第一指令具有第一操作数，第二操作数和第三操作数，所述第一操作数指定存储四个 SHA指出，第二操作数指定存储与第五SHA1状态相结合的多个SHA1消息输入的第二存储位置。 所述处理器还包括执行单元，其响应于所述第一指令而耦合到所述指令解码器，以使用所述第一和第二操作数获得的所述SHA1状态和从所述第一和第二操作数获得的所述消息输入执行至少四轮所述SHA1循环操作， 逻辑功能在第三个操作数中指定。
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公开(公告)号：US20170093823A1
公开(公告)日：2017-03-30
申请号：US14865751
申请日：2015-09-25
申请人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
CPC分类号： H04L63/061 , G06F12/1416 , G06F21/78 , G06F2212/1052 , H04L63/0442
摘要： Address information may be secured by sharing a key between a host central processing unit subsystem and an external memory. Information about how write addresses are modified may be exchanged between said subsystem and said memory. The write addresses for the same memory location are changed each time a write accesses the address.
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49.发明申请INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS SECURE HASH ALGORITHMS 有权指令处理器，方法和系统来处理安全的哈希算法公开(公告)号：US20140185793A1
公开(公告)日：2014-07-03
申请号：US13729502
申请日：2012-12-28
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F21/602 , G06F21/64 , G06F21/72
摘要： A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.
摘要翻译： 方面的方法包括接收指令。 该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。 该指令指示第二打包数据的第二来源。 第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。 该方法还包括响应于指令将结果存储在由指令指示的目的地中。 结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。
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50.发明授权Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction 有权响应于单个指令执行旋转和异或的系统，设备和方法公开(公告)号：US09128698B2
公开(公告)日：2015-09-08
申请号：US13631242
申请日：2012-09-28
CPC分类号： G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value.
摘要翻译： 这里公开的是在计算机处理器中执行的响应于单个XOR和旋转指令执行旋转和异或的系统，装置和方法，其中旋转和XOR指令包括第一和第二源操作数，目的地操作数和 即时价值。
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