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49 条记录 (耗时 0.029 秒)

    Semiconductor memory device having a plurality of writing and reading ports for decreasing hardware amount
    42.
    发明授权
    Semiconductor memory device having a plurality of writing and reading ports for decreasing hardware amount 失效
    半导体存储器件具有用于降低硬件量的多个写入和读取端口

    公开(公告)号：US5355335A

    公开(公告)日：1994-10-11

    申请号：US903518

    申请日：1992-06-24

    申请人： Akira Katsuno

    发明人： Akira Katsuno

    IPC分类号： G11C8/16 ,  G11C7/00

    CPC分类号： G11C8/16

    摘要： A semiconductor memory device, that has a plurality of writing ports and reading ports comprises a first data latch portion, at least one second data latch portions, and communication units. The first data latch portion is directly accessible by externally entering an address signal, and the second data latch portions are parallel connected to the first data latch portion. The communication units is used to access one of the first and second data latch portions. Therefore, according to the semiconductor memory device of the present invention, the amount of hardware of a register file of the processor employing parallel processing and local register architecture can be significantly reduced by providing the first data latch portion and at least one or more of the second data latch portions having communication units and accessing one of the first and second data latch portions.

    摘要翻译： 具有多个写入端口和读取端口的半导体存储器件包括第一数据锁存部分，至少一个第二数据锁存器部分和通信单元。 第一数据锁存部分可以通过外部输入地址信号直接访问，第二数据锁存部分并联连接到第一数据锁存部分。 通信单元用于访问第一和第二数据锁存部分中的一个。 因此，根据本发明的半导体存储器件，通过提供第一数据锁存部分和第一数据锁存部分中的至少一个或多个，可以显着地减少采用并行处理和本地寄存器结构的处理器的寄存器文件的硬件量 第二数据锁存部分具有通信单元并访问第一和第二数据锁存部分之一。

    Floating point operation unit in division and square root operations
    48.
    发明授权
    Floating point operation unit in division and square root operations 失效
    浮点运算单位划分和平方根操作

    公开(公告)号：US4999801A

    公开(公告)日：1991-03-12

    申请号：US374299

    申请日：1989-06-30

    申请人： Akira Katsuno

    发明人： Akira Katsuno

    IPC分类号： G06F7/52 ,  G06F7/535 ,  G06F7/552

    CPC分类号： G06F7/535 ,  G06F7/5525 ,  G06F2207/5355 ,  G06F2207/5356 ,  G06F7/4873 ,  G06F7/49936 ,  G06F7/49957

    摘要： A floating point operation unit comprises an exponent operation circuit, a sign operation circuit and a mantissa operation circuit. The mantissa operation circuit comprises a fixed point multiplier, a first right shifter, an incrementer, a rounding off controller, a second right shifter, and further, an inversion circuit between the first right shifter and the incrementer. By controlling the inversion circuit and the rounding off controler when one operation of an iterative approximation in a division or a square root operation is executed, the number of cycles in the above operation is reduced, and as a result, the operating speed is increased.