公开(公告)号：US20080279025A1

公开(公告)日：2008-11-13

申请号：US11568003

申请日：2005-04-21

申请人： Victor Martinus Gerardus Van Acht ,  Albert W. Marsman ,  Boon Keat Chong ,  Nicolaas Lambert ,  Pierre Hermanus Woerlee ,  Teunis Jan Ikkink ,  Aalbert Stek ,  Hans Marc Bert Boeve ,  Gavin Nicholas Phillips

发明人： Victor Martinus Gerardus Van Acht ,  Albert W. Marsman ,  Boon Keat Chong ,  Nicolaas Lambert ,  Pierre Hermanus Woerlee ,  Teunis Jan Ikkink ,  Aalbert Stek ,  Hans Marc Bert Boeve ,  Gavin Nicholas Phillips

IPC分类号： G11C7/02 ,  H03M7/00

CPC分类号： G11C7/14 ,  G11C7/1006 ,  G11C2207/104 ,  G11C2207/2254 ,  G11C2211/5634

摘要： A memory (10) is organized as a matrix rows and columns of memory cell circuits (100) and comprises bit line conductors (12) coupled to rows of the memory cells (100). A sensing circuit (14) is coupled to the bit line conductors (12). The sensing circuit (14) is arranged to form respective data signals, each by comparing a respective signal from a plurality of the bit line conductors (12) with a reference level that is common for the bit line conductors (12). A reference level selection circuit (16) with inputs coupled to the plurality of bit line conductors (12) is arranged to control the reference level. The reference level selection circuit (16) selects the reference level dependent on respective analog signal levels on the plurality of the bit line conductors (12), so that analog signal levels from at least respective ones of the plurality of bit line conductors (12) lie on respective sides of the reference level.

摘要翻译： 存储器（10）被组织为存储单元电路（100）的矩阵行和列，并且包括耦合到存储器单元（100）的行的位线导体（12）。 感测电路（14）耦合到位线导体（12）。 感测电路（14）被布置成通过将来自多个位线导体（12）的相应信号与位线导体（12）共用的基准电平进行比较来形成相应的数据信号。 具有耦合到多个位线导体（12）的输入的参考电平选择电路（16）被布置成控制参考电平。 参考电平选择电路（16）根据多个位线导体（12）上的相应模拟信号电平选择参考电平，使得来自多个位线导体（12）中的至少相应的模拟信号电平， 位于参考水平的相应侧。

公开(公告)号：US20080252338A1

公开(公告)日：2008-10-16

申请号：US12088735

申请日：2006-10-04

申请人： Victor Martinus Gerardus Van Acht ,  Nicolaas Lambert ,  Andrei Mijiritskii ,  Pierre Hermanus Woerlee

发明人： Victor Martinus Gerardus Van Acht ,  Nicolaas Lambert ,  Andrei Mijiritskii ,  Pierre Hermanus Woerlee

IPC分类号： H03K3/00

CPC分类号： H03K19/01721 ,  H03K19/09441

摘要： An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.

摘要翻译： 由单阈值和单导电类型的电路元件组成的放大器/缓冲器，包括用于接收用于缓冲/放大的一个或多个输入的输入级，并且提供中间级以控制放大器/缓冲器的输出。 中间信号被提供给升压电路，该升压电路被配置为当所述信号超过预定值时升高所述信号。 放大器/缓冲器还具有用于至少接收所述信号并提供放大/缓冲输出的输出级。

公开(公告)号：US06743682B2

公开(公告)日：2004-06-01

申请号：US10100595

申请日：2002-03-18

申请人： Pierre Hermanus Woerlee ,  Jurriaan Schmitz ,  Andreas Hubertus Montree

发明人： Pierre Hermanus Woerlee ,  Jurriaan Schmitz ,  Andreas Hubertus Montree

IPC分类号： H01L21336

CPC分类号： H01L21/76895 ,  H01L29/4966 ,  H01L29/66537 ,  H01L29/66545

摘要： In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 is applied defining the area of the gate structure 21. Subsequently, a dielectric layer 18 is applied in such a way, that the thickness of the dielectric layer 18 next to the patterned layer 10 is substantially equally large or larger than the height of the patterned layer 10, which dielectric layer 18 is removed over part of its thickness until the patterned layer 10 is exposed. Then, the patterned layer 10 is subjected to a material removing treatment, thereby forming a recess 19 in the dielectric layer 18, and a contact window 28,29 is provided in the dielectric layer. A conductive layer 30 is applied filling the recess 19 and the contact window 28,29, which conductive layer 30 is subsequently shaped into the gate structure 21 and a contact structure 26,27 establishing an electrical contact with the surface 2 of the semiconductor body 1.

摘要翻译： 在制造半导体器件的方法中，该半导体器件包括半导体本体1，半导体本体1在表面2处设置有包括栅极结构21的晶体管，施加限定栅极结构21的区域的图案化层10.随后，介电层18 以这样的方式施加，图案化层10旁边的电介质层18的厚度基本上等于或大于图案化层10的高度，该图案层10的厚度在其厚度的一部分上被去除，直到图案化层 层10暴露。 然后，对图案层10进行材料去除处理，从而在电介质层18中形成凹部19，并且在电介质层中设置接触窗28,29。 填充导电层30，其填充凹部19和接触窗28,29，该导电层30随后成形为栅极结构21，以及与半导体主体1的表面2建立电接触的接触结构26,27 。

公开(公告)号：US06461908B2

公开(公告)日：2002-10-08

申请号：US09829796

申请日：2001-04-10

申请人： Peter Adriaan Stolk ,  Pierre Hermanus Woerlee ,  Mathijs Johan Knitel ,  Anja Catharina Maria Carolina Van Brandenburg

发明人： Peter Adriaan Stolk ,  Pierre Hermanus Woerlee ,  Mathijs Johan Knitel ,  Anja Catharina Maria Carolina Van Brandenburg

IPC分类号： H01L218238

CPC分类号： H01L29/66575 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device including a PMOS transistor (6) and an NMOS transistor (5) comprises the steps of: (a) providing a semiconductor substrate (1) having a P-well region (3), which is to be provided with the NMOS transistor (5), and an N-well region (2), which is to be provided with the PMOS transistor (6); (b) forming gate electrodes (8) on the P-well region (3) and the N-well region (2); (c) applying a hard mask (10), which covers either the P-well region (3) or the N-well region (2); (d) implanting a source and a drain in the region that is not covered by the hard mask (10), followed by heat activation; (e) implanting pocket implants in the region that is not covered by the hard mask (10), followed by heat activation; (f) removing the hard mask (10).

摘要翻译： 制造包括PMOS晶体管（6）和NMOS晶体管（5）的半导体器件的方法包括以下步骤：（a）提供具有P阱区域（3）的半导体衬底（1） 设置有NMOS晶体管（5）以及设置有PMOS晶体管（6）的N阱区域（2）;（b）在P阱区域（3）上形成栅电极（8） 和N阱区域（2）;（c）施加覆盖P阱区域（3）或N阱区域（2）的硬掩模（10）;（d）植入源极和 在未被硬掩模（10）覆盖的区域内排出，然后进行热激活;（e）在未被硬掩模（10）覆盖的区域内植入口袋植入物，随后热激活;（f） 去除硬掩模（10）。