公开(公告)号：US11984479B2

公开(公告)日：2024-05-14

申请号：US17177556

申请日：2021-02-17

Applicant: Analog Devices International Unlimited Company

Inventor： Dennis A. Dempsey ,  Andrew Christopher Linehan ,  Seamus P. Whiston ,  David J. Rohan

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/1041 ,  H01L29/0649 ,  H01L29/66537

Abstract: The present disclosure relates to a field effect transistor (FET) structure. The FET structure has a substrate, an active region, a dielectric layer provided over a channel of the active region and a gate provided over the dielectric layer. The active region comprises a source, a drain and the channel provided between the source and the drain. The active region is surrounded by an isolation trench, such that width edges of the channel are directly adjacent to the isolation trench. Current paths run between the source and the drain, through the channel. The FET is configured such that current paths running proximal to the channel edges are reduced or weaker in comparison to a dominant current path running through a center of the channel. One or more of the channel, the dielectric layer or the substrate can be modified or adapted to provide the reduced and dominant current paths. In one example, the center of the channel away from the edges has a first doping concentration of a first conductivity type, and the sides of the channel along the channel edges have a second doping concentration of the first conductivity type, where the second doping concentration is greater than the first doping concentration. In another example, the dielectric layer is thicker over the sides of the channel and thinner over the center of the channel. In another example, regions of the substrate below the sides of the channel have a higher doping concentration than a region of the substrate below the center of the channel. In some examples, the FET structure has both the dielectric layer of different thicknesses and the different doping concentrations in the channel and/or the substrate.

公开(公告)号：US20230253456A1

公开(公告)日：2023-08-10

申请号：US18135426

申请日：2023-04-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

CPC classification number: H01L29/1083 ,  H01L21/74 ,  H01L21/84 ,  H01L21/265 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/4238 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/6681 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20190237473A1

公开(公告)日：2019-08-01

申请号：US16201584

申请日：2018-11-27

Applicant: MIE FUJITSU SEMICONDUCTOR LIMITED

Inventor： Taiji Ema ,  Makoto Yasuda

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H01L21/266 ,  H01L21/265 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/26513 ,  H01L21/266 ,  H01L27/11573 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device is disclosed. A gate electrode is provided above a semiconductor substrate. A sidewall insulation film is provided to the gate electrode. Source and drain regions are provided in the substrate and contain first conductive impurities. A first semiconductor region is provided in the substrate, is on a source region side, and has a concentration of the first conductive impurities lower than the source region. A second semiconductor region is provided in the substrate, is on a drain region side, and has a concentration of the first conductive impurities lower than the drain and first semiconductor regions. A channel region is provided between the first and second semiconductor regions. A third semiconductor region is provided under the channel region, and includes second conductive impurities higher in concentration than the channel region. Information is stored by accumulating charges in the sidewall insulation film.

公开(公告)号：US20180366557A1

公开(公告)日：2018-12-20

申请号：US15956477

申请日：2018-04-18

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/165 ,  H01L29/423

CPC classification number: H01L29/66356 ,  H01L21/0257 ,  H01L29/0676 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0895 ,  H01L29/165 ,  H01L29/42312 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7311 ,  H01L29/7391

Abstract: After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.

公开(公告)号：US20180261683A1

公开(公告)日：2018-09-13

申请号：US15963598

申请日：2018-04-26

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Dalong Zhao ,  Teymur Bakhishev ,  Lance Scudder ,  Paul E. Gregory ,  Michael Duane ,  U.C. Sridharan ,  Pushkar Ranade ,  Lucian Shifren ,  Thomas Hoffmann

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10

CPC classification number: H01L29/66537 ,  H01L21/265 ,  H01L21/283 ,  H01L21/823412 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66477

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element

公开(公告)号：US20180166323A1

公开(公告)日：2018-06-14

申请号：US15802721

申请日：2017-11-03

Applicant: Cypress Semiconductor Corporation

Inventor： Ching-Huang LU ,  Lei Xue ,  Kenichi Ohtsuka ,  Simon Siu-Sing Chan ,  Rinji Sugino

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L29/792 ,  H01L29/788

CPC classification number: H01L21/76237 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823481 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/66484 ,  H01L29/66537 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the buried trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

公开(公告)号：US09978839B2

公开(公告)日：2018-05-22

申请号：US15628925

申请日：2017-06-21

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki Yamamoto ,  Hideki Makiyama ,  Toshiaki Iwamatsu ,  Takaaki Tsunomura

IPC: H01L21/00 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/74 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US09934975B2

公开(公告)日：2018-04-03

申请号：US14494447

申请日：2014-09-23

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Qiuxia Xu ,  Yanbo Zhang ,  Hong Yang

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28105 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545

Abstract: An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer.

公开(公告)号：US20180083119A1

公开(公告)日：2018-03-22

申请号：US15271264

申请日：2016-09-21

Applicant: Pedro Guillen

Inventor： Pedro Guillen

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/225 ,  H01L21/324 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66537 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/1041 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7833

Abstract: A method for manufacturing a semiconductor device exhibiting improved short channel effects and increased current driving ability is disclosed. The method includes the steps of: providing a substrate of a first conductivity-type, e.g., P-type; forming a gate insulating layer on the substrate; forming a gate electrode on the gate insulating layer; forming a gate cap insulating layer on the gate electrode; introducing inactive ions of the first conductivity-type into the first conductivity-type semiconductor substrate at both sides of the gate electrode, so as to form amorphous regions; forming first impurity regions of the first conductivity-type near the amorphous regions; and forming second impurity regions of a second conductivity-type, e.g., N-type, in the substrate at both sides of the gate electrode. The method also includes forming source and drain regions of the second conductivity-type in the substrate. The amorphous regions are formed by ion implantation of the inactive ions while the first and second impurity regions and the source and drain regions are formed by ion implantation of active ions. Inactive ions are ions which, after implantation into the amorphous regions, assume an atomic or molecular state in which they act neither as acceptors nor donors. Conversely, active ions act as acceptors or donors after implantation.

公开(公告)号：US09922971B2

公开(公告)日：2018-03-20

申请号：US15204338

申请日：2016-07-07

Applicant: Texas Instruments Incorporated

Inventor： Himadri Sekhar Pal ,  Shashank S. Ekbote ,  Youn Sung Choi

IPC: H01L21/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L21/265 ,  H01L21/266 ,  H01L29/167 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823418 ,  H01L21/823456 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/42372 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.