公开(公告)号：US11456357B2

公开(公告)日：2022-09-27

申请号：US16024125

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Anupama Bowonder ,  William Hsu ,  Szuya S. Liao ,  Mehmet Onur Baykan ,  Tahir Ghani

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/20

Abstract: Techniques are disclosed for forming integrated circuits configured with self-aligned isolation walls and alternate channel materials. The alternate channel materials in such integrated circuits provide improved carrier mobility through the channel. In an embodiment, an isolation wall is between sets of fins, at least some of the fins including an alternate channel material. In such cases, the isolation wall laterally separates the sets of fins, and the alternate channel material provides improved carrier mobility. For instance, in the case of an NMOS device the alternate channel material is a material optimized for electron flow, and in the case of a PMOS device the alternate channel material is a material optimized for hole flow.

公开(公告)号：US11233152B2

公开(公告)日：2022-01-25

申请号：US16017966

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Leonard P. Guler ,  Dax M. Crum ,  Tahir Ghani

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

公开(公告)号：US20200006478A1

公开(公告)日：2020-01-02

申请号：US16023511

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： William Hsu ,  Biswajeet Guha ,  Leonard Guler ,  Souvik Chakrabarty ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.