公开(公告)号：US20080112441A1

公开(公告)日：2008-05-15

申请号：US12014138

申请日：2008-01-15

申请人： David Hathaway ,  Kerim Kalafala

发明人： David Hathaway ,  Kerim Kalafala

IPC分类号： H04J3/06

CPC分类号： H04L41/14 ,  H04L43/0852 ,  H04L43/16

摘要： A method of performing node-based static timing analysis on a digital network and a program storage device for implementing the method, wherein the method comprises partitioning timing delays in the digital network into portions attributable to a factor of interest and portions attributable to other factors; multiplying the timing delays by different weights based on the factor of interest to produce weighted timing delays; and using the multiplied timing delays to determine a relative impact of the factor of interest on the various paths in the digital network. The method further comprises setting arrival times of timing signals at digital network path start points to zero and identifying digital network paths whose timing delays are dominated by a particular factor of interest. The different weights comprise any of a positive weight, a negative weight, and a zero weight.

摘要翻译： 一种在数字网络上执行基于节点的静态时序分析的方法和用于实现该方法的程序存储设备，其中该方法包括将数字网络中的定时延迟分成可归因于其他因素的关注因素和部分; 基于感兴趣的因素将定时延迟乘以不同的权重以产生加权定时延迟; 并且使用相乘的定时延迟来确定感兴趣因素对数字网络中各种路径的相对影响。 该方法还包括将数字网络路径起点处的定时信号的到达时间设置为零，并且识别其定时延迟由特定感兴趣的因素支配的数字网络路径。 不同的重量包括正重量，负重量和零重量中的任何一种。

公开(公告)号：US08776004B2

公开(公告)日：2014-07-08

申请号：US13006450

申请日：2011-01-14

申请人： Frank Borkam ,  Hemlata Gupta ,  David J. Hathaway ,  Kerim Kalafala ,  Vasant Rao ,  Alex Rubin

发明人： Frank Borkam ,  Hemlata Gupta ,  David J. Hathaway ,  Kerim Kalafala ,  Vasant Rao ,  Alex Rubin

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.

摘要翻译： 使用反向合并定时确定时钟整形和其他数字电路的非控制输入端的静态时序分析余量包括：在逻辑设计中选择一个或多个具有多个输入并使用反向合并的电路; 从所述多个输入中识别所选择的电路的控制输入; 以及为所述电路的至少一个非控制输入确定可基于所述控制和非控制输入的到达时间之间的差异来驱动设计优化的定时值。

公开(公告)号：US20120185810A1

公开(公告)日：2012-07-19

申请号：US13006450

申请日：2011-01-14

申请人： Frank Borkam ,  Hemlata Gupta ,  David J. Hathaway ,  Kerim Kalafala ,  Vasant Rao ,  Alex Rubin

发明人： Frank Borkam ,  Hemlata Gupta ,  David J. Hathaway ,  Kerim Kalafala ,  Vasant Rao ,  Alex Rubin

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.

摘要翻译： 使用反向合并定时确定时钟整形和其他数字电路的非控制输入端的静态时序分析余量包括：在逻辑设计中选择一个或多个具有多个输入并使用反向合并的电路; 从所述多个输入中识别所选择的电路的控制输入; 以及为所述电路的至少一个非控制输入确定可基于所述控制和非控制输入的到达时间之间的差异来驱动设计优化的定时值。

公开(公告)号：US20100318951A1

公开(公告)日：2010-12-16

申请号：US12484293

申请日：2009-06-15

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/504 ,  G06F2217/84

摘要： A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing.

摘要翻译： 一种用于在集成电路设计的静态时序分析期间调整基于历史的延迟变化的系统和方法。 该方法可以包括通过延迟变异性的基于历史的组件的变异源获得信息，以及变异源与一个或多个有界设备历史之间的关系。 然后，为集成电路设计的至少一个信号输入历史界限，并且通过集成电路设计的至少一个第一段将集成电路设计的至少一个信号计算和传播历史界限。 此外，该方法可以包括从至少一个传播的历史界限评估集成电路设计的至少一个第二段的设备历史界限，以及基于所评估的设备历史界限，调整至少一个 基于历史的延迟变异性和时间传播。

公开(公告)号：US20080163147A1

公开(公告)日：2008-07-03

申请号：US11619349

申请日：2007-01-03

申请人： James C. Gregerson ,  Kerim Kalafala ,  Alexander Suess

发明人： James C. Gregerson ,  Kerim Kalafala ,  Alexander Suess

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Run-time reduction is achieved in timing performance of a logical design, such as a digital integrated circuit. A portion of the logical design that is expected to be stable with respect to timing performance, such as a clock tree, is identified. Timing sensitivities, including sensitivities to sources of variability, of the identified portion of the logical design are determined at a given instant. The timing sensitivities of the identified portion of the logical design are saved for re-use. The saved timing sensitivities are re-used throughout the timing analysis and in subsequent timing analyses.

摘要翻译： 在诸如数字集成电路之类的逻辑设计的时序性能上实现了运行时间的减少。 识别期望相对于定时性能稳定的逻辑设计的一部分，例如时钟树。 在给定的时刻确定逻辑设计的识别部分的时间灵敏度，包括对变异源的敏感性。 逻辑设计的识别部分的定时灵敏度被保存以供重新使用。 保存的定时灵敏度在整个时序分析和随后的时序分析中被重新使用。

公开(公告)号：US07353477B2

公开(公告)日：2008-04-01

申请号：US10709327

申请日：2004-04-28

申请人： David J. Hathaway ,  Kerim Kalafala

发明人： David J. Hathaway ,  Kerim Kalafala

IPC分类号： G06F17/50

CPC分类号： H04L41/14 ,  H04L43/0852 ,  H04L43/16

摘要： A method of performing node-based static timing analysis on a digital network and a program storage device for implementing the method, wherein the method comprises partitioning timing delays in the digital network into portions attributable to a factor of interest and portions attributable to other factors; multiplying the timing delays by different weights based on the factor of interest to produce weighted timing delays; and using the multiplied timing delays to determine a relative impact of the factor of interest on the various paths in the digital network. The method further comprises setting arrival times of timing signals at digital network path start points to zero and identifying digital network paths whose timing delays are dominated by a particular factor of interest. The different weights comprise any of a positive weight, a negative weight, and a zero weight.

摘要翻译： 一种在数字网络上执行基于节点的静态时序分析的方法和用于实现该方法的程序存储设备，其中该方法包括将数字网络中的定时延迟分成可归因于其他因素的关注因素和部分; 基于感兴趣的因素将定时延迟乘以不同的权重以产生加权定时延迟; 并且使用相乘的定时延迟来确定感兴趣因素对数字网络中各种路径的相对影响。 该方法还包括将数字网络路径起点处的定时信号的到达时间设置为零，并且识别其定时延迟由特定感兴趣的因素支配的数字网络路径。 不同的重量包括正重量，负重量和零重量中的任何一种。

公开(公告)号：US20050243869A1

公开(公告)日：2005-11-03

申请号：US10709327

申请日：2004-04-28

申请人： David Hathaway ,  Kerim Kalafala

发明人： David Hathaway ,  Kerim Kalafala

IPC分类号： H04J3/06 ,  H04L12/24

CPC分类号： H04L41/14 ,  H04L43/0852 ,  H04L43/16

摘要： A method of performing node-based static timing analysis on a digital network and a program storage device for implementing the method, wherein the method comprises partitioning timing delays in the digital network into portions attributable to a factor of interest and portions attributable to other factors; multiplying the timing delays by different weights based on the factor of interest to produce weighted timing delays; and using the multiplied timing delays to determine a relative impact of the factor of interest on the various paths in the digital network. The method further comprises setting arrival times of timing signals at digital network path start points to zero and identifying digital network paths whose timing delays are dominated by a particular factor of interest. The different weights comprise any of a positive weight, a negative weight, and a zero weight.

摘要翻译： 一种在数字网络上执行基于节点的静态时序分析的方法和用于实现该方法的程序存储设备，其中该方法包括将数字网络中的定时延迟分成可归因于其他因素的关注因素和部分; 基于感兴趣的因素将定时延迟乘以不同的权重以产生加权定时延迟; 并且使用相乘的定时延迟来确定感兴趣因素对数字网络中各种路径的相对影响。 该方法还包括将数字网络路径起点处的定时信号的到达时间设置为零，并且识别其定时延迟由特定感兴趣的因素支配的数字网络路径。 不同的重量包括正重量，负重量和零重量中的任何一种。