公开(公告)号：US08447961B2

公开(公告)日：2013-05-21

申请号：US12708288

申请日：2010-02-18

Applicant: Anindya Saha ,  Manish Kumar ,  Hemant Mallapur ,  Santhosh Billava ,  Viji Rajangam

Inventor： Anindya Saha ,  Manish Kumar ,  Hemant Mallapur ,  Santhosh Billava ,  Viji Rajangam

IPC: G06F9/40

CPC classification number: G06F9/325 ,  G06F9/30065 ,  G06F9/381 ,  G06F9/3853

Abstract: A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction buffer size. A program memory receives a Program Memory address to fetch an instruction packet. The program memory is closely coupled with the instruction buffer size to implement the zero overhead software pipelined (SFP) loop. The size of the zero overhead software pipelined (SFP) loop can exceed the instruction buffer size. A CPU control register includes a block count and an iteration count. The block count is loaded into a block counter and counts the plurality of instructions executed in the SFP loop, and the iteration count is loaded into an iteration counter and counts a number of iterations of the SFP loop based on the block count.

Abstract translation: 实现零开销软件流水线（SFP）循环的系统包括具有N个执行时隙的超长指令字（VLIW）处理器。 VLIW处理器并行执行多个指令，而不受指令缓冲器大小的任何限制。 程序存储器接收程序存储器地址以获取指令包。 程序存储器与指令缓冲区大小紧密相连，以实现零开销软件流水线（SFP）循环。 零开销软件流水线（SFP）循环的大小可以超过指令缓冲区大小。 CPU控制寄存器包括块计数和迭代计数。 块计数被加载到块计数器中并对在SFP循环中执行的多个指令进行计数，并且将迭代计数加载到迭代计数器中，并且基于块计数对SFP循环的迭代次数进行计数。