公开(公告)号：US20240103874A1

公开(公告)日：2024-03-28

申请号：US17951859

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Niranjan Kumar Soundararajan ,  Sreenivas Subramoney ,  Jayesh Gaur

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/381 ,  G06F9/30065 ,  G06F9/325

Abstract: Methods and apparatus for instruction elimination through hardware driven memoization of loop instances. A hardware-based loop memoization technique learns repeating sequences of loops and transparently removes instructions for the loop instructions from instruction sequences while making their output available to dependent instructions as if the loop instructions had been executed. A path-based predictor is implemented at the front-end to predict these loop instances and remove their instructions from instruction sequences. A novel memoization prediction micro-operation (Uop) is inserted into the instruction sequence for instances of loops that are predicted to be memoized. The memoization prediction Uop is used to compare the input signature (expected set of input values for the loop) with the actual signature to determine correct and incorrect predictions. The input signature learnt is based on all live-ins of a loop, both explicit register-based live-ins as well as loads to memory in the loop body that determine code path and outputs.

公开(公告)号：US11928474B2

公开(公告)日：2024-03-12

申请号：US17832350

申请日：2022-06-03

Applicant: Microsoft Technology Licensing, LLC

Inventor： Rami Mohammad Al Sheikh ,  Saransh Jain ,  Michael Scott McIlvaine ,  Daren Eugene Streett

IPC: G06F9/38 ,  G06F9/32

CPC classification number: G06F9/3844 ,  G06F9/325 ,  G06F9/381

Abstract: Selectively updating branch predictors for loops executed from loop buffers is disclosed herein. In some aspects, a branch predictor update circuit of a processor is configured to detect a loop comprising a plurality of loop instructions in an instruction stream, and to determine that the loop is stored within a loop buffer circuit of the processor. The branch predictor update circuit is further configured to determine a count of potential history register updates to the history register for the plurality of loop instructions, and to determine whether the count of potential history register updates exceeds a size of the history register. The branch predictor update circuit is also configured to, responsive to determining that the count of potential history register updates does not exceed the size of the history register, update a branch predictor of the branch predictor circuit based on the plurality of loop instructions.

公开(公告)号：US20230418764A1

公开(公告)日：2023-12-28

申请号：US18460772

申请日：2023-09-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Quang Bui ,  Joseph Raymond Michael Zbiciak

IPC: G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/48 ,  G06F17/16 ,  H03H17/06 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009

CPC classification number: G06F12/1045 ,  G06F15/7807 ,  G06F9/345 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F9/30065 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30149 ,  G06F9/3818 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/48 ,  G06F17/16 ,  G06F9/30032 ,  G06F9/30072 ,  G06F9/3887 ,  H03H17/0664 ,  G06F9/3856 ,  G06F9/30098 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/3802 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009 ,  G06F11/10 ,  G06F9/3822 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/30145

Abstract: In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.

公开(公告)号：US11829300B2

公开(公告)日：2023-11-28

申请号：US17958503

申请日：2022-10-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Mujibur Rahman

IPC: G06F7/06 ,  G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/48 ,  G06F17/16 ,  H03H17/06 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009 ,  G06F15/78

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/3016 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3818 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/781 ,  G06F15/7807 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.

公开(公告)号：US20230350813A1

公开(公告)日：2023-11-02

申请号：US18348047

申请日：2023-07-06

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Mujibur Rahman

IPC: G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/48 ,  G06F17/16 ,  H03H17/06 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009

CPC classification number: G06F12/1045 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F9/30065 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30149 ,  G06F9/3818 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/48 ,  G06F17/16 ,  G06F9/30032 ,  G06F9/30072 ,  G06F9/3887 ,  H03H17/0664 ,  G06F9/3855 ,  G06F9/30098 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/3802 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009 ,  G06F11/10 ,  G06F9/3822 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F15/7807

Abstract: Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication unit. Each of these multiplication units includes carry-save adder circuitry with a respective outputs, partial product alignment multiplexing logic coupled to the outputs of the associated carry-save adder circuitry. The processor further comprises communication paths coupled between the outputs of the carry-save adder circuitry of the first multiplication unit and the partial product alignment multiplexing logic of the second multiplication unit. In other configurations, each of the first and second multiplication units may include one or more instances of masking logic, one or more instances of a multiplier array coupled to the associated instance(s) of masking logic, and one or more instances of a multiplexer set coupled to the associated instance(s) of multiplier array(s). Each of multiplexer set instance(s) of a particular multiplication unit is coupled to the carry-save adder circuitry of that multiplication unit.

公开(公告)号：US11755484B2

公开(公告)日：2023-09-12

申请号：US14752418

申请日：2015-06-26

Applicant: Microsoft Technology Licensing, LLC

Inventor： Jan S. Gray ,  Douglas C. Burger ,  Aaron L. Smith

IPC: G06F12/0831 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F12/128

CPC classification number: G06F12/0833 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3846 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3891 ,  G06F11/30 ,  G06F12/128 ,  G06F2212/621

Abstract: Apparatus and methods are disclosed for throttling processor operation in block-based processor architectures. In one example of the disclosed technology, a block-based instruction set architecture processor includes a plurality of processing cores configured to fetch and execute a sequence of instruction blocks. Each of the processing cores includes function resources for performing operations specified by the instruction blocks. The processor further includes a core scheduler configured to allocate functional resources for performing the operations. The functional resources are allocated for executing the instruction blocks based, at least in part, on a performance metric. The performance metric can be generated dynamically or statically based on branch prediction accuracy, energy usage tolerance, and other suitable metrics.

公开(公告)号：US11734194B2

公开(公告)日：2023-08-22

申请号：US17713002

申请日：2022-04-04

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Mujibur Rahman

IPC: G06F9/30 ,  G06F12/1045 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/48 ,  G06F17/16 ,  H03H17/06 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009 ,  G06F15/78

CPC classification number: G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/3016 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3818 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/781 ,  G06F15/7807 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

Abstract: A method is provided that includes performing, by a processor in response to a dual issue multiply instruction, multiplication of operands of the dual issue multiply instruction using multiplication units comprised in a data path of the processor and configured to operate together to determine a product of the operands, and storing, by the processor, the product in a storage location indicated by the dual issue multiply instruction.

公开(公告)号：US20180181405A1

公开(公告)日：2018-06-28

申请号：US15390194

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Jayesh IYER ,  Sergey P. SCHERBININ ,  Alexander Y. OSTANEVICH ,  Dmitry M. MASLENNIKOV ,  Denis G. MOTIN ,  Alexander V. ERMOLOVICH ,  Andrey CHUDNOVETS ,  Sergey A. ROZHKOV ,  Boris A. BABAYAN

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3885 ,  G06F8/445 ,  G06F8/4452 ,  G06F8/452 ,  G06F9/3001 ,  G06F9/30058 ,  G06F9/30065 ,  G06F9/3009 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30127 ,  G06F9/30138 ,  G06F9/30141 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/381 ,  G06F9/384 ,  G06F9/3851

Abstract: An apparatus includes a register file and a binary translator to create a plurality of strands and a plurality of iteration windows, where each iteration window of the plurality of iteration windows is allocated a set of continuous registers of the register file. The apparatus further includes a buffer to store strand documentation for a strand from the plurality of strands, where the strand documentation for the strand is to include an indication of a current register base for the strand. The apparatus further includes an execution circuit to execute an instruction to update the current register base for the strand in the strand documentation for the strand based on a fixed step value and an iteration window size.

公开(公告)号：US09946545B2

公开(公告)日：2018-04-17

申请号：US12926415

申请日：2010-11-16

Applicant: James Nolan Hardage ,  Glen Andrew Harris ,  Mark Carpenter Glass

Inventor： James Nolan Hardage ,  Glen Andrew Harris ,  Mark Carpenter Glass

IPC: G06F15/00 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F5/06

CPC classification number: G06F9/3806 ,  G06F5/065 ,  G06F9/381

Abstract: A loop buffer is provided with a main store 26 and an auxiliary store 28. The main store 26 stores micro-operation instructions. The auxiliary store 28 has fewer entries than the main store 26 and stores target addresses for predicted taken branch instructions stored within the main store 26. Read control circuitry serves to control reading from the main store and from an auxiliary store such that target addresses are read from the auxiliary store in association with the predicted taken branch instructions read from the main store.

公开(公告)号：US09898297B2

公开(公告)日：2018-02-20

申请号：US14830704

申请日：2015-08-19

Applicant: Hyperion Core, Inc.

Inventor： Martin Vorbach ,  Frank May ,  Markus Weinhardt

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/45

CPC classification number: G06F9/3836 ,  G06F8/443 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30065 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30134 ,  G06F9/30189 ,  G06F9/381 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

Abstract: A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.