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    Method of determining lethality of defects in circuit pattern inspection method of selecting defects to be reviewed and inspection system of circuit patterns involved with the methods
    41.
    发明授权
    Method of determining lethality of defects in circuit pattern inspection method of selecting defects to be reviewed and inspection system of circuit patterns involved with the methods 有权
    确定电路图案检查缺陷检测方法的选择方法及其检查方法

    公开(公告)号：US06334097B1

    公开(公告)日：2001-12-25

    申请号：US09225513

    申请日：1999-01-06

    申请人： Yasuhiro Yoshitake ,  Masataka Shiba ,  Atsushi Shimoda

    发明人： Yasuhiro Yoshitake ,  Masataka Shiba ,  Atsushi Shimoda

    IPC分类号： G06F1132

    CPC分类号： H01L22/20 ,  G01N21/95607 ,  H01L2924/0002 ,  H01L2924/00

    摘要： From the coordinate data of defects detected on the circuit patterns, the areas where the defects belong are identified. The sizes of the defects detected are compared with the data to determine the lethality to thereby determine the lethality of the defects. Further, the severity of the defects is calculated from the sizes of the defects to thereby select the review object in the descending order of the severity. Thereby, when inspecting the circuit patterns on a semiconductor wafer or the like, the lethality of the defects can automatically be determined even though the review is not carried out, enhancing the efficiency of the inspection. To perform the review with efficiency, the defects to be reviewed are automatically selected, while the quality of the inspection itself is maintained.

    摘要翻译： 根据在电路图案上检测到的缺陷的坐标数据，识别缺陷所在的区域。 将检测到的缺陷的大小与数据进行比较以确定致死率，从而确定缺陷的致死率。 此外，根据缺陷的大小计算缺陷的严重性，从而以严重性的降序选择检查对象。因此，当检查半导体晶片等上的电路图案时，缺陷的致死性可以 即使不进行审查，自动确定，提高检查效率。 为了有效地进行审查，将自动选择要检查的缺陷，同时保持检查质量。