公开(公告)号：US06563148B2

公开(公告)日：2003-05-13

申请号：US09828981

申请日：2001-04-10

申请人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

发明人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

IPC分类号： H01L2710

CPC分类号： H01L21/31053 ,  H01L21/76229

摘要： The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.

公开(公告)号：US06299314B1

公开(公告)日：2001-10-09

申请号：US09494785

申请日：2000-01-31

申请人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

发明人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823443 ,  H01L21/823475

摘要： Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of silicide structure are are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.

摘要翻译： 提供了一种半导体器件及其制造方法，其中将SAC结构的MOS晶体管和硅化物结构的MOS晶体管组合在一起。 栅极结构（GT11〜GT13）的栅极电极（3）被上部氮化膜（4）和侧壁氮化物膜（5）覆盖。 因此，为了形成接触孔（CH1，CH2）选择性地除去作为氧化膜的层间绝缘膜（10），不会去除上部氮化物膜（4）和侧壁氮化物膜（5），从而防止栅电极 3）不被暴露。 特别地，在栅极结构（GT11和GT12）中，即使接触孔（CH1）位于任一侧，也不会在导体层（CL1）和栅电极（3）之间产生短路。 因此，栅极结构（GT11和GT12）可以被布置而不受接触孔（CH1）的对准边缘的限制，并且可以减小栅极之间的距离以获得高集成度。