公开(公告)号：US06753246B2

公开(公告)日：2004-06-22

申请号：US10419770

申请日：2003-04-22

申请人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

发明人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

IPC分类号： H01L214763

CPC分类号： H01L21/31053 ,  H01L21/76229

摘要： The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.

摘要翻译： 半导体器件包括半导体衬底，并且在半导体衬底中的元件隔离区域中具有间距小于第一A / A虚设图形的间距的第一有源区A / A虚拟图案和第二A / A虚拟图案 。 第一A / A虚拟图案的放置和第二A / A虚拟图案的放置在单独的步骤中进行。 半导体衬底可以被划分成多个网格区域，并且可以根据网格区域被位于其中的元素图案占据的区域而将虚设图案放置在每个网格区域中。

公开(公告)号：US06563148B2

公开(公告)日：2003-05-13

申请号：US09828981

申请日：2001-04-10

申请人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

发明人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

IPC分类号： H01L2710

CPC分类号： H01L21/31053 ,  H01L21/76229

摘要： The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.

公开(公告)号：US06461946B2

公开(公告)日：2002-10-08

申请号：US09843859

申请日：2001-04-30

申请人： Takeshi Kitani ,  Katsumi Eikyu ,  Masao Sugiyama

发明人： Takeshi Kitani ,  Katsumi Eikyu ,  Masao Sugiyama

IPC分类号： H01L2104

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L21/76218 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892

摘要： Both P type and N type impurities are implanted from a plurality of directions. The tilt angle &thgr; of the implantation direction against the normal of the main surface of a semiconductor substrate is fixed to 10°, and the deflection angle &phgr; is set to such four directions (X, X+90°, X+180°, and X+270°, where X is an arbitrary angle) that projecting components of a vector indicating the implantation direction are opposed to each other on two lines that cross each other at right angles along the main surface of the semiconductor substrate. Thereby, the dependency of the breakdown voltage of element isolation on the direction of a well boundary is suppressed to realize a high breakdown voltage of element isolation in all directions.

摘要翻译： 从多个方向注入P型和N型杂质。 将注入方向相对于半导体衬底的主表面的法线的倾斜角度θ固定为10°，将偏转角度phi设定为这样的四个方向（X，X + 90°，X + 180°， 在沿着半导体基板的主表面成直角交叉的两条线上投影指示注入方向的矢量的分量相对的X + 270°，其中X是任意角度）。 因此，抑制元件隔离的击穿电压对阱边界的方向的依赖性，以实现元件隔离在所有方向上的高击穿电压。

公开(公告)号：US06424042B1

公开(公告)日：2002-07-23

申请号：US09505990

申请日：2000-02-17

申请人： Takeshi Kitani

发明人： Takeshi Kitani

IPC分类号： H01L2398

CPC分类号： H01L21/76816 ,  H01L21/76813 ,  H01L21/7684 ,  H01L23/522 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/05556 ,  H01L2224/06517 ,  H01L2224/17517 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/04941 ,  H01L2924/05042

摘要： An interlayer film layer is formed on an (N−1)-th interconnection Layer via a barrier film, and an N-th interconnection layer is formed on the interlayer film layer. An interconnection having a Damascene structure is formed in the interconnection layer and the interlayer film layer. The interconnection has an wiring portion having a narrow line width and a pad portion having a wide line width. A recess corresponding to the wiring portion and the pad portion is provided in an insulating film of the interconnection layer. A recess corresponding to the pad portion is provided in an insulating film of the interlayer film layer. A barrier metal and a metal film are deposited in both the recesses, and unnecessary portions of the barrier metal and the metal film are removed by CMP, to form a multilayer interconnection structure.

摘要翻译： 在第（N-1）布线层上经由阻挡膜形成层间膜层，在层间膜层上形成第N互连层。 在互连层和层间膜层中形成具有镶嵌结构的互连。 互连具有线宽窄的布线部分和线宽宽的焊盘部分。 在互连层的绝缘膜中设置与布线部分和焊盘部分相对应的凹部。 在该层间膜层的绝缘膜上设置与该焊盘部对应的凹部。 在两个凹部中沉积阻挡金属和金属膜，通过CMP除去阻挡金属和金属膜的不必要部分，形成多层互连结构。

公开(公告)号：US06555887B1

公开(公告)日：2003-04-29

申请号：US09368345

申请日：1999-08-05

申请人： Takeshi Kitani ,  Takeru Matsuoka ,  Masayoshi Shirahata

发明人： Takeshi Kitani ,  Takeru Matsuoka ,  Masayoshi Shirahata

IPC分类号： H01L31119

CPC分类号： H01L21/76886 ,  H01L21/28061 ,  H01L21/76801 ,  H01L21/76838

摘要： A semiconductor device with a polycide interconnection including a refractory metal silicide film improved in adherence with an interlayer insulation film, and a method of fabricating such a semiconductor device are provided. The local impurity concentration of a tungsten silicide film in the proximity of the interface between an interlayer oxide film and the tungsten silicide film is set to 5×1019 atms/cm3-2×1022 atms/cm3.

摘要翻译： 提供了具有提高了与层间绝缘膜的粘附性的难熔金属硅化物膜的具有多晶硅互连的半导体器件，以及制造这种半导体器件的方法。 在层间氧化膜和硅化钨膜之间的界面附近的硅化钨膜的局部杂质浓度设定为5×1019atms / cm 2 -2×10 22 atms / cm 3。