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41.发明授权公开(公告)号：US06490689B1
公开(公告)日：2002-12-03
申请号：US09337157
申请日：1999-06-21
IPC分类号： G06F104
CPC分类号： G06F1/14
摘要： A physical clock is expanded to enhance its precision. Existing instructions are capable of using the enhanced physical clock. Execution of an instruction begins, which places a value of the expanded physical clock in a physical clock field of a clock representation. The physical clock field is, however, unable to accommodate the value provided by the expanded physical clock. Thus, that value encroaches upon another predefined field of the clock representation. Completion of the instruction is therefore delayed such that the value provided by the expanded physical clock can be accommodated in the clock representation and a correct value for the another predefined field can be provided.
摘要翻译： 物理时钟被扩展以提高其精度。 现有指令能够使用增强的物理时钟。 开始执行指令，将扩展的物理时钟的值置于时钟表示的物理时钟字段中。 然而，物理时钟字段无法适应扩展的物理时钟提供的值。 因此，该值侵占了时钟表示的另一个预定义字段。 指令的完成因此被延迟，使得扩展的物理时钟提供的值可以被容纳在时钟表示中，并且可以提供另一个预定义字段的正确值。
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42.发明授权Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code 失效地址比特解码用于RXE指令格式的相同加法器电路，具有与RX格式相同的XBD位置和解码的扩展操作码
公开(公告)号：US6105126A
公开(公告)日：2000-08-15
申请号：US70359
申请日：1998-04-30
申请人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
发明人： Mark Anthony Check , Ronald M. Smith, Sr. , John Stephen Liptay , Eric Mark Schwarz , Timothy John Slegel , Charles Franklin Webb
CPC分类号： G06F9/355 , G06F9/30185
摘要： A computer processor floating point processor six cycle pipeline system where instruction text is fetched prior to the first cycle and decoded during the first cycle for the fetched particular instruction and the base (B) and index (X) register values are read for use in address generation. RXE Instructions are of the RX-type but extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine the exact format from the first 8 bits of the operation code alone. ESA/390 instructions SS, RR; RX; S; RRE; RI; and the new RXE instructions have a format which can be used for fixed point processing as well as floating point processing where instructions of the RXE format have their R1, X2, B2, and D2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates the correct information to said X-B-D adder. During the second cycle the address add of B+X+Displacement is performed and sent to the cache processor's, and during the third and fourth cycles the cache is respectively accessed and data is returned, and during a fifth cycle execution of the fetched instruction occurs with the result putaway in a sixth cycle.
摘要翻译： 计算机处理器浮点处理器六循环流水线系统，其中指令文本在第一周期之前获取并且在第一周期期间被解码用于所提取的特定指令，并且基准（B）和索引（X）寄存器值被读取用于地址 代。 RXE指令是RX型，但通过将操作码的扩展置于指令格式的前四个字节之外进行扩展，并以这样的方式分配操作码，使得机器可以从前8位确定确切的格式 的操作代码。 ESA / 390指令SS，RR; RX; S; RRE; RI; 并且新的RXE指令具有可用于固定点处理以及浮点处理的格式，其中RXE格式的指令在所述指令寄存器中的相同位置具有其R1，X2，B2和D2字段，如 RX格式，使处理器能够从操作代码的前8位确定正在解码的指令是RXE格式指令和RXE格式指令的寄存器索引扩展，之后它将正确信息锁定到所述XBD加法器 。 在第二周期期间，执行B + X +位移的地址添加并发送到高速缓存处理器，并且在第三和第四周期期间，分别访问高速缓存并返回数据，并且在第五周期期间执行所取出的指令 结果放在第六个周期。
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43.发明授权Multi-function instruction that determines whether functions are installed on a system 有权确定功能是否安装在系统上的多功能指令公开(公告)号：US08661231B2
公开(公告)日：2014-02-25
申请号：US13487929
申请日：2012-06-04
IPC分类号： G06F9/30
CPC分类号： G06F9/45504 , G06F9/30007 , G06F9/30018 , G06F9/30094 , G06F9/3017 , G06F9/30181 , G06F9/342 , G06F21/72 , H04L9/08
摘要： A method, system and program product for executing a multi-function instruction in an emulated computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system.
摘要翻译： 一种用于在仿真计算机系统中执行多功能指令的方法，系统和程序产品，其通过多功能指令来指定能力查询或执行一个或多个可选功能的选定功能，其中所选功能 是安装的可选功能，其中能力查询确定在计算机系统上安装一个或多个可选功能的哪些可选功能。
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44.发明授权Detection of potential need to use a larger data format in performing floating point operations 有权检测潜在需要在执行浮点运算时使用较大的数据格式公开(公告)号：US08560591B2
公开(公告)日：2013-10-15
申请号：US11740165
申请日：2007-04-25
CPC分类号： G06F9/30036 , G06F7/491 , G06F9/30003 , G06F9/30014 , G06F9/30105 , G06F9/3861 , G06F9/45504 , G06F2207/4911
摘要： Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.
摘要翻译： 检测浮点运算的结果是否安全。 检查结果的特征以确定结果是安全的还是潜在的不安全的，如用户定义的。 提供了一个指导，以便于检测安全或潜在不安全的结果。
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公开(公告)号：US08386756B2
公开(公告)日：2013-02-26
申请号：US13083760
申请日：2011-04-11
IPC分类号： G06F7/38
CPC分类号： G06F9/30014 , G06F9/3001 , G06F9/3802 , G06F9/3836
摘要： A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.
摘要翻译： 新的zSeries浮点单元具有融合的多重加法数据流，能够支持两种架构，并以融合功能的RRF和RXF格式融合MULTIPLY和ADD以及Multiply和SUBTRACT。 二进制和十六进制浮点指令都支持共6种格式。 浮点单元能够对每个循环执行十六进制或二进制的加法指令，延迟时间为5个周期。 这支持两种具有自己偏见的内部格式的架构。 这消除了格式转换周期，并优化了数据流的宽度。 该单元针对支持每个周期的乘法/减法的十六进制和二进制浮点架构进行了优化。
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46.发明授权Performing a perform timing facility function instruction for sychronizing TOD clocks 有权执行用于同步TOD时钟的执行定时设备功能指令公开(公告)号：US08135978B2
公开(公告)日：2012-03-13
申请号：US12540261
申请日：2009-08-12
申请人： Eberhard Engler , Mark S. Farrell , Klaus Meissner , Ronald M. Smith, Sr. , Evangelyn K. Smith, legal representative , Mark A. Check
CPC分类号： G06F1/14
摘要： A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD clock with TOD clocks of other computer systems. The computer system comprises a memory; and, a processor in communications with the computer memory. The processor is capable of performing a PTFF instruction comprising: obtaining a function code specified in a first general register, the function code for identifying any one of a query function or a control function to be performed; obtaining, from a second general register, a memory address of a parameter block; responsive to the function code specifying a query function, storing timing information of the computer system in the parameter block according to the specified query function; responsive to the function code specifying a control function, using timing information obtained from the parameter block to perform the specified control function; and setting a condition code value indicating an outcome of the specified function.
摘要翻译： 一种用于执行用于使TOD时钟与其他计算机系统的TOD时钟同步的计算机系统的时间（TOD）时钟的执行定时设备（PTFF）指令的系统，方法和计算机程序产品。 计算机系统包括存储器; 以及与计算机存储器通信的处理器。 处理器能够执行PTFF指令，包括：获得在第一通用寄存器中指定的功能代码，用于识别要执行的查询功能或控制功能中的任何一个的功能代码; 从第二通用寄存器获取参数块的存储器地址; 响应于指定查询功能的功能代码，根据指定的查询功能将计算机系统的定时信息存储在参数块中; 响应于指定控制功能的功能代码，使用从参数块获得的定时信息来执行指定的控制功能; 并设置指示指定功能的结果的条件代码值。
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47.发明授权公开(公告)号：US07949858B2
公开(公告)日：2011-05-24
申请号：US12363825
申请日：2009-02-02
IPC分类号： G06F7/38
CPC分类号： G06F9/30014 , G06F9/3001 , G06F9/3802 , G06F9/3836
摘要： A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.
摘要翻译： 新的zSeries浮点单元具有融合的多重加法数据流，能够支持两种架构，并以融合功能的RRF和RXF格式融合MULTIPLY和ADD以及Multiply和SUBTRACT。 二进制和十六进制浮点指令都支持共6种格式。 浮点单元能够对每个循环执行十六进制或二进制的加法指令，延迟时间为5个周期。 这支持两种具有自己偏见的内部格式的架构。 这消除了格式转换周期，并优化了数据流的宽度。 该单元针对支持每个周期的乘法/减法的十六进制和二进制浮点架构进行了优化。
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公开(公告)号：US07861093B2
公开(公告)日：2010-12-28
申请号：US11468501
申请日：2006-08-30
CPC分类号： G06F9/526 , G06F9/524 , G06F2209/521
摘要： The management of data access is facilitated. A loop only if changed locking facility is provided, in which reads and updates of the data being managed are permitted, unless an update to the data completes during the execution of the read or update routine. As long as an update to the data has not completed during a processor's execution of the read or update routine, access is permitted.
摘要翻译： 数据访问管理方便。 只有在提供了改变的锁定设备时，才允许循环，除非在执行读取或更新程序期间对数据的更新完成。 只要数据的更新在处理器执行读取或更新程序期间尚未完成，则允许访问。
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49.发明授权公开(公告)号：US07765389B2
公开(公告)日：2010-07-27
申请号：US11740185
申请日：2007-04-25
IPC分类号： G06F9/455
CPC分类号： G06F9/3865 , G06F9/30003 , G06F9/30094 , G06F9/45504
摘要： Exception handling is simulated. An exception simulator is employed to simulate exceptions generated from routines simulating operations. The exception simulator provides an indication of the exception and invokes an interruption, when appropriate. The exception simulator includes an instruction invoked to handle the exception and any interruption.
摘要翻译： 模拟异常处理。 使用异常模拟器来模拟从仿真操作的例程产生的异常。 异常模拟器提供异常的指示，并在适当时调用中断。 异常模拟器包括调用以处理异常和任何中断的指令。
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公开(公告)号：US07058837B2
公开(公告)日：2006-06-06
申请号：US10435970
申请日：2003-05-12
申请人： David A. Elko , Richard K. Errickson , Steven N. Goss , Dan F. Greiner , Carol B. Hernandez , Ronald M. Smith, Sr. , David H. Surman
发明人： David A. Elko , Richard K. Errickson , Steven N. Goss , Dan F. Greiner , Carol B. Hernandez , Ronald M. Smith, Sr. , David H. Surman
CPC分类号： G06F9/546
摘要： A method for providing a message-time-ordering facility is disclosed. The method comprises initiating the message-timer ordering facility for a message at a sender system. Initiating includes setting a delay variable to zero. The message is sent to a receiver system in response to initiating the message-time-ordering facility. Sending the message includes marking the message with a first departure time-stamp responsive to a sender system clock and transmitting the message to the receiver system. The message is received at the at the receiver system, receiving includes delaying the processing of the message until the time on a receiver system clock is greater than the first departure time-stamp and recording a time associated with the delaying the processing of the message in the delay variable. A response to the message is sent to the sender system in response to receiving the message. Sending the response includes marking the response with a second departure time-stamp responsive to the receiver system clock if the delay variable is equal to zero and transmitting the response to the sender system. The response is received at the sender system. Receiving the response includes delaying the processing of the response if the delay variable is equal to zero until the time on the sender system clock is greater than the second departure time-stamp and recording a time associated with the delaying the processing of the response in the delay variable.
摘要翻译： 公开了一种提供消息时间排序设施的方法。 该方法包括在发送者系统处发起消息的消息定时器排序设施。 启动包括将延迟变量设置为零。 响应于启动消息时间排序设施，该消息被发送到接收机系统。 发送消息包括响应于发送者系统时钟的第一起始时间戳来标记消息并将消息发送到接收机系统。 消息在接收机系统处被接收，接收包括延迟消息的处理，直到接收机系统时钟的时间大于第一个出发时间戳，并且记录与将消息的处理延迟相关联的时间 延迟变量。 响应于接收到该消息，对该消息的响应被发送到发送者系统。 发送响应包括响应于接收机系统时钟的第二个出发时间戳来标记响应，如果延迟变量等于零并将响应发送到发送器系统。 发送方系统收到响应。 如果延迟变量等于0，则接收响应包括延迟响应的处理，直到发送方系统时钟的时间大于第二个出发时间戳，并记录与延迟处理响应相关的时间 延迟变量。
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