公开(公告)号：US20150309930A1

公开(公告)日：2015-10-29

申请号：US14694415

申请日：2015-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Mehrdad Nourani

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/6032 ,  Y02D10/13

Abstract: With the increasing demand for improved processor performance, memory systems have been growing increasingly larger to keep up with this performance demand. Caches, which dictate the performance of memory systems are often the focus of improved performance in memory systems, and the most common techniques used to increase cache performance are increased size and associativity. Unfortunately, these methods yield increased static and dynamic power consumption. In this invention, a technique is shown that reduces the power consumption in associative caches with some improvement in cache performance. The architecture shown achieves these power savings by reducing the number of ways queried on each cache access, using a simple hash function and no additional storage, while skipping some pipe stages for improved performance. Up to 90% reduction in power consumption with a 4.6% performance improvement was observed.

Abstract translation: 随着对改进处理器性能的日益增长的需求，内存系统越来越大，以适应这种性能需求。 规定存储器系统性能的高速缓存通常是内存系统性能改进的重点，而用于增加缓存性能的最常用技术是增加大小和关联性。 不幸的是，这些方法产生了静态和动态功耗的增加。 在本发明中，示出了一种减少关联高速缓存中的功耗的技术，同时具有缓存性能的一些改进。 所示的架构通过减少每个缓存访问查询的方式，使用简单的散列函数和无额外的存储，同时跳过一些管道级以提高性能，从而实现了这些功耗。 观察到功耗降低了90％，性能提高了4.6％。