-
公开(公告)号：US20240195707A1
公开(公告)日：2024-06-13
申请号：US18394888
申请日：2023-12-22
申请人： Intel Corporation
IPC分类号： H04L41/5003 , G06F9/455 , G06F12/084 , G06F12/0864 , H04L43/08 , H04L47/70 , H04L67/568
CPC分类号： H04L41/5003 , G06F9/45558 , G06F12/084 , G06F12/0864 , H04L43/08 , H04L47/82 , H04L67/568 , G06F2009/4557 , G06F2009/45583 , G06F2009/45595 , G06F2212/1024 , G06F2212/154 , G06F2212/6032
摘要： Technologies for managing cache quality of service (QoS) include a compute node that includes a network interface controller (NIC) configured to identify a total amount of available shared cache ways of a last level cache (LLC) of the compute node and identify a destination address for each of a plurality of virtual machines (VMs) managed by the compute node. The NIC is further configured to calculate a recommended amount of cache ways for each workload type associated with VMs based on network traffic to be received by the NIC and processed by each of the VMs, wherein the recommended amount of cache ways includes a recommended amount of hardware I/O LLC cache ways and a recommended amount of isolated LLC cache ways usable to update a cache QoS register that includes the recommended amount of cache ways for each workload type. Other embodiments are described herein.
-
公开(公告)号：US11940930B2
公开(公告)日：2024-03-26
申请号：US17875572
申请日：2022-07-28
IPC分类号： G06F9/30 , G06F9/54 , G06F11/10 , G06F12/02 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F12/128 , G06F13/16 , G06F15/80 , G11C5/06 , G11C7/10 , G11C7/22 , G11C29/42 , G11C29/44
CPC分类号： G06F12/128 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/127 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.
-
公开(公告)号：US20240080374A1
公开(公告)日：2024-03-07
申请号：US18505841
申请日：2023-11-09
申请人： OPEN TEXT INC.
IPC分类号： H04L67/5682 , G06F12/0802 , G06F12/0864 , G06F12/0875 , G06F12/12 , G06F12/128 , G06F16/957 , G06F21/60 , G06F21/62 , H04L67/561 , H04L67/5683
CPC分类号： H04L67/5682 , G06F12/0802 , G06F12/0864 , G06F12/0875 , G06F12/12 , G06F12/128 , G06F16/9574 , G06F21/604 , G06F21/6218 , H04L67/561 , H04L67/5683 , G06F2212/6032 , G06F2221/2141
摘要： Embodiments disclosed herein relate to systems and methods for providing a smart cache. In embodiments, a variable time to live (TTL) may be calculated and associated with data as it is stored in a cache. The variable TTL may be calculated based upon reputation and/or category information related to the source of the data. The reputation and/or category information may include TTL modifiers for adjusting the TTL for data from a particular data source that is stored in the cache. In further embodiments, a feedback method may be employed to update reputation and/or category information for a particular data source.
-
公开(公告)号：US11888710B2
公开(公告)日：2024-01-30
申请号：US16140938
申请日：2018-09-25
申请人： Intel Corporation
IPC分类号： H04L41/5003 , G06F12/084 , G06F9/455 , H04L43/08 , H04L47/70 , G06F12/0864 , H04L67/568
CPC分类号： H04L41/5003 , G06F9/45558 , G06F12/084 , G06F12/0864 , H04L43/08 , H04L47/82 , H04L67/568 , G06F2009/4557 , G06F2009/45583 , G06F2009/45595 , G06F2212/1024 , G06F2212/154 , G06F2212/6032
摘要： Technologies for managing cache quality of service (QoS) include a compute node that includes a network interface controller (NIC) configured to identify a total amount of available shared cache ways of a last level cache (LLC) of the compute node and identify a destination address for each of a plurality of virtual machines (VMs) managed by the compute node. The NIC is further configured to calculate a recommended amount of cache ways for each workload type associated with VMs based on network traffic to be received by the NIC and processed by each of the VMs, wherein the recommended amount of cache ways includes a recommended amount of hardware I/O LLC cache ways and a recommended amount of isolated LLC cache ways usable to update a cache QoS register that includes the recommended amount of cache ways for each workload type. Other embodiments are described herein.
-
公开(公告)号：US20240020242A1
公开(公告)日：2024-01-18
申请号：US18362015
申请日：2023-07-31
IPC分类号： G06F12/126 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
CPC分类号： G06F12/126 , G06F2212/6042 , G06F12/0891 , G06F9/546 , G06F12/0215 , G06F12/0238 , G06F12/0811 , G06F12/128 , G06F12/082 , G06F12/0804 , G06F9/3001 , G06F9/30047 , G11C7/106 , G11C7/1087 , G11C29/42 , G11C29/44 , G06F11/1064 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/1605 , G06F12/121 , G06F12/0292 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/222 , G11C7/1075 , G11C7/1078 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G11C5/066 , G11C7/10 , G11C7/1015 , G06F15/8069 , G06F12/0802 , G06F9/30043 , G06F2212/1021 , G06F2212/608 , G06F2212/6032 , G06F2212/1024 , G06F2212/62 , G06F2212/1016 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F12/0888
摘要： Methods, apparatus, systems and articles of manufacture to reduce bank pressure using aggressive write merging are disclosed. An example apparatus includes a first cache storage; a second cache storage; a store queue coupled to at least one of the first cache storage and the second cache storage and operable to: receive a first memory operation; process the first memory operation for storing the first set of data in at least one of the first cache storage and the second cache storage; receive a second memory operation; and prior to storing the first set of data in the at least one of the first cache storage and the second cache storage, merge the first memory operation and the second memory operation.
-
公开(公告)号：US11822474B2
公开(公告)日：2023-11-21
申请号：US17830257
申请日：2022-06-01
申请人： FLC Global, Ltd.
发明人： Sehat Sutardja
IPC分类号： G06F12/0811 , G06F12/0864 , G11C11/406 , G06F12/0804 , G06F12/0868 , G06F12/0897 , G06F3/06 , G06F12/10 , G06F12/1027 , G06F9/4401 , G06F12/0813 , G06F12/0862 , G06F12/06
CPC分类号： G06F12/0811 , G06F3/061 , G06F3/0613 , G06F3/0638 , G06F3/0655 , G06F3/0656 , G06F3/0679 , G06F3/0683 , G06F9/4406 , G06F12/0804 , G06F12/0813 , G06F12/0862 , G06F12/0864 , G06F12/0868 , G06F12/0897 , G06F12/10 , G06F12/1027 , G11C11/40607 , G06F12/0607 , G06F2212/1016 , G06F2212/1021 , G06F2212/152 , G06F2212/154 , G06F2212/161 , G06F2212/171 , G06F2212/20 , G06F2212/202 , G06F2212/214 , G06F2212/22 , G06F2212/222 , G06F2212/251 , G06F2212/305 , G06F2212/50 , G06F2212/60 , G06F2212/608 , G06F2212/6022 , G06F2212/6032 , G06F2212/62 , Y02D10/00
摘要： A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.
-
公开(公告)号：US11775446B2
公开(公告)日：2023-10-03
申请号：US17472811
申请日：2021-09-13
IPC分类号： G06F12/0811 , G06F12/02 , G06F12/0897 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802 , G06F12/126
CPC分类号： G06F12/0811 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/082 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/128 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/106 , G11C7/1015 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/608 , G06F2212/6032 , G06F2212/6042 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.
-
公开(公告)号：US20230281126A1
公开(公告)日：2023-09-07
申请号：US18309893
申请日：2023-05-01
IPC分类号： G06F12/0811 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802 , G06F12/126
CPC分类号： G06F12/0811 , G06F9/3001 , G06F9/30043 , G06F9/30047 , G06F9/546 , G06F11/1064 , G06F12/0215 , G06F12/0238 , G06F12/0292 , G06F12/0802 , G06F12/0804 , G06F12/0806 , G06F12/0815 , G06F12/082 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0884 , G06F12/0888 , G06F12/0891 , G06F12/0895 , G06F12/0897 , G06F12/12 , G06F12/121 , G06F12/126 , G06F12/128 , G06F13/1605 , G06F13/1642 , G06F13/1673 , G06F13/1689 , G06F15/8069 , G11C5/066 , G11C7/10 , G11C7/1015 , G11C7/106 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/222 , G11C29/42 , G11C29/44 , G06F2212/1016 , G06F2212/1021 , G06F2212/1024 , G06F2212/1041 , G06F2212/1044 , G06F2212/301 , G06F2212/454 , G06F2212/6032 , G06F2212/6042 , G06F2212/608 , G06F2212/62
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.
-
公开(公告)号：US20230236983A1
公开(公告)日：2023-07-27
申请号：US18117974
申请日：2023-03-06
发明人： Richard C. Murphy
IPC分类号： G06F12/0864 , G06F12/0811 , G06F9/30 , G11C7/10 , G11C11/4091 , G11C11/4096 , G06F12/0895 , G06F12/084
CPC分类号： G06F12/0864 , G06F12/0811 , G06F9/30036 , G11C7/1006 , G11C11/4091 , G11C11/4096 , G06F12/0895 , G06F12/084 , G06F2212/283 , G06F2212/6032 , G11C11/4094
摘要： The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.
-
公开(公告)号：US10019370B2
公开(公告)日：2018-07-10
申请号：US15200572
申请日：2016-07-01
IPC分类号： G06F12/02 , G06F12/0864 , G06F12/121 , G06F12/0873 , G06F12/0895 , G06F12/128
CPC分类号： G06F12/0864 , G06F12/0873 , G06F12/0895 , G06F12/121 , G06F12/128 , G06F2212/1016 , G06F2212/1056 , G06F2212/281 , G06F2212/305 , G06F2212/313 , G06F2212/6032 , G06F2212/6082
摘要： A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)-way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.
-
-
-
-
-
-
-
-
-
搜索结果
238 条记录 (耗时 0.022 秒)
