公开(公告)号：US4068188A

公开(公告)日：1978-01-10

申请号：US768840

申请日：1977-02-15

申请人： Takao Yokoyama

发明人： Takao Yokoyama

IPC分类号： H03L7/08 ,  H04N5/12 ,  H03B3/04

CPC分类号： H04N5/126 ,  H03L7/08

摘要： Phase locked loop (PLL) circuit comprises, a phase detector including first and second cascade-connected differential pairs of transistors constituting an analog multiplier with each one of the differential pair transistors supplied with two inputs, a low pass filter for converting the detection output into a D.C. control voltage, and an emitter-coupled multivibrator including constant current sources for determining the oscillation frequency with a timing capacitor. The PLL circuit is provided with constant current adjusting means for variably setting or determining the current through a constant current source connected to the second differential pair of transistors and the currents through the current sources determining the oscillation frequency in a correlated manner through a common variable resistor. Thereby, dispersions in the loop gain of the PLL circuit are reduced.

摘要翻译： 锁相环（PLL）电路包括：相位检测器，包括构成模拟乘法器的第一和第二级联连接的差分对晶体管，每个差分对晶体管被提供有两个输入;低通滤波器，用于将检测输出转换成 DC控制电压和发射极耦合多谐振荡器，其包括用定时电容器确定振荡频率的恒定电流源。 PLL电路设置有恒流调节装置，用于可变地设置或确定通过连接到第二差分晶体管对的恒流源的电流，并且通过电流源的电流通过公共可变电阻器以相关方式确定振荡频率 。 从而减小了PLL电路的环路增益中的分散。