公开(公告)号：US07790543B2

公开(公告)日：2010-09-07

申请号：US11972941

申请日：2008-01-11

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

IPC分类号： H01L21/8238

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode and semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are separated by a gap that is filled by a gate dielectric layer. The gate dielectric layer may be composed of thermal oxide layers grown on adjacent sidewalls of the semiconductor body and gate electrode, in combination with an optional deposited dielectric material that fills the remaining gap between the thermal oxide layers.

摘要翻译： 适用于在较高电压下工作的金属氧化物半导体场效应晶体管（MOSFET）的器件结构及其形成方法。 使用绝缘体上半导体（SOI）衬底形成的MOSFET包括半导体本体中与栅电极自对准的沟道。 由SOI衬底的单晶SOI层形成的栅电极和半导体本体由被栅极电介质层填充的间隙分开。 栅极电介质层可以由在半导体主体和栅电极的相邻侧壁上生长的热氧化物层组合，并与填充热氧化物层之间的剩余间隙的任选沉积的电介质材料组合。

公开(公告)号：US07790524B2

公开(公告)日：2010-09-07

申请号：US11972949

申请日：2008-01-11

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

IPC分类号： H01L21/00

CPC分类号： H01L29/7881 ,  H01L29/66825

摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM) and methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes. The device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a floating gate electrode, a semiconductor body, and a control gate electrode separated from the semiconductor body by the floating gate electrode. The floating gate electrode, the control gate electrode, and the semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are respectively separated by dielectric layers. The dielectric layers may each be composed of thermal oxide layers grown on confronting sidewalls of the semiconductor body, the floating gate electrode, and the control gate electrode. An optional deposited dielectric material may fill any remaining gap between either pair of the thermal oxide layers.

摘要翻译： 用于非易失性随机存取存储器（NVRAM）中的存储器单元的装置和设计结构以及使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法。 使用绝缘体上半导体（SOI）衬底形成的器件结构包括通过浮栅电极与半导体本体分离的浮栅电极，半导体本体和控制栅电极。 由SOI衬底的单晶SOI层形成的浮置栅电极，控制栅电极和半导体本体分别由电介质层分离。 介电层可以各自由在半导体本体，浮栅电极和控制栅电极的相对侧壁上生长的热氧化物层组成。 任选沉积的介电材料可以填充任何一对热氧化物层之间的剩余间隙。

公开(公告)号：US20100032761A1

公开(公告)日：2010-02-11

申请号：US12188381

申请日：2008-08-08

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

IPC分类号： H01L27/12

CPC分类号： H01L27/088 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1207

摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

摘要翻译： 第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。 第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。 第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。 还提供了用于半导体结构的设计结构。

公开(公告)号：US20090250772A1

公开(公告)日：2009-10-08

申请号：US12099175

申请日：2008-04-08

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/423 ,  H01L29/66575

摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

摘要翻译： 提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。 该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。 有源区具有不同于第一导电类型的第二导电类型。 接触区域与有源区域电接触。 该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。

公开(公告)号：US20090179266A1

公开(公告)日：2009-07-16

申请号：US11972941

申请日：2008-01-11

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

IPC分类号： H01L27/12 ,  H01L21/782

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode and semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are separated by a gap that is filled by a gate dielectric layer. The gate dielectric layer may be composed of thermal oxide layers grown on adjacent sidewalls of the semiconductor body and gate electrode, in combination with an optional deposited dielectric material that fills the remaining gap between the thermal oxide layers.

摘要翻译： 适用于在较高电压下工作的金属氧化物半导体场效应晶体管（MOSFET）的器件结构及其形成方法。 使用绝缘体上半导体（SOI）衬底形成的MOSFET包括半导体本体中与栅电极自对准的沟道。 由SOI衬底的单晶SOI层形成的栅电极和半导体本体由被栅极电介质层填充的间隙分开。 栅极电介质层可以由在半导体主体和栅电极的相邻侧壁上生长的热氧化物层组合，并与填充热氧化物层之间的剩余间隙的任选沉积的电介质材料组合。

公开(公告)号：US20090179251A1

公开(公告)日：2009-07-16

申请号：US11972949

申请日：2008-01-11

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L29/66825

摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM) and methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes. The device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a floating gate electrode, a semiconductor body, and a control gate electrode separated from the semiconductor body by the floating gate electrode. The floating gate electrode, the control gate electrode, and the semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are respectively separated by dielectric layers. The dielectric layers may each be composed of thermal oxide layers grown on confronting sidewalls of the semiconductor body, the floating gate electrode, and the control gate electrode. An optional deposited dielectric material may fill any remaining gap between either pair of the thermal oxide layers.

摘要翻译： 用于非易失性随机存取存储器（NVRAM）中的存储器单元的装置和设计结构以及使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法。 使用绝缘体上半导体（SOI）衬底形成的器件结构包括通过浮栅电极与半导体本体分离的浮栅电极，半导体本体和控制栅电极。 由SOI衬底的单晶SOI层形成的浮置栅电极，控制栅电极和半导体本体分别由电介质层分离。 介电层可以各自由在半导体本体，浮栅电极和控制栅电极的相对侧壁上生长的热氧化物层组成。 任选沉积的介电材料可以填充任何一对热氧化物层之间的剩余间隙。

公开(公告)号：US08916467B2

公开(公告)日：2014-12-23

申请号：US13116396

申请日：2011-05-26

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

IPC分类号： H03K3/01 ,  H01L21/336 ,  G06F17/50 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/84

摘要： A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.

摘要翻译： 具有与底部半导体层相反的导电类型的掺杂接触区域设置在底部半导体层中的掩埋绝缘体层的下方。 至少一个导电通孔结构从互连级金属线延伸穿过中间线（MOL）电介质层，顶部半导体层中的浅沟槽隔离结构，以及掩埋绝缘体层和掺杂接触区域。 掺杂接触区域被偏置在处于或接近RF开关中的峰值电压的电压，该电压去除感应电荷层内的少数电荷载流子。 少数电荷载体通过掺杂接触区域和至少一个导电通孔结构排出。 诱导电荷层中的移动电荷的快速放电减少了RF开关中的谐波产生和信号失真。 还提供了用于半导体结构的设计结构。

公开(公告)号：US08349697B2

公开(公告)日：2013-01-08

申请号：US13537334

申请日：2012-06-29

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti ,  Yun Shi

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  William R. Tonti ,  Yun Shi

IPC分类号： H01L21/76

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.

摘要翻译： 一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。 门通过气隙与身体的至少一部分分离。 气隙也在第一平面。

公开(公告)号：US20120264275A1

公开(公告)日：2012-10-18

申请号：US13537334

申请日：2012-06-29

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  William R. Tonti ,  Yun Shi

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  William R. Tonti ,  Yun Shi

IPC分类号： H01L21/762

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane.

摘要翻译： 一种场效应晶体管（FET），包括形成在第一平面中的漏极，形成在第一平面中的源极，形成在第一平面中，在漏极和源极之间的沟道以及形成在第一平面中的栅极。 门通过气隙与身体的至少一部分分离。 气隙也在第一平面。

公开(公告)号：US20120132992A1

公开(公告)日：2012-05-31

申请号：US13367646

申请日：2012-02-07

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

IPC分类号： H01L27/12

CPC分类号： H01L27/088 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1207

摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

摘要翻译： 第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。 第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。 第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。 还提供了用于半导体结构的设计结构。