公开(公告)号：US08255196B2

公开(公告)日：2012-08-28

申请号：US12197572

申请日：2008-08-25

申请人： William W. Walker ,  Subodh M. Reddy ,  Ranjeez Murgai

发明人： William W. Walker ,  Subodh M. Reddy ,  Ranjeez Murgai

IPC分类号： G06F17/50

CPC分类号： G06F1/10 ,  G06F17/5036 ,  G06F2217/62

摘要： A system and method for constructing a clock tree based on replica stages is described. The system and method may comprise determining a size of an input buffer for driving a load capacitance of the output buffer based on a fanout, determining a wire width and a wire length based on the size of the output buffer, the fanout and a replica stage mathematical model, and connecting the output buffer and the corresponding input buffer to a conductor routed on one or more predetermined metal layers and having the wire length and the wire width. The conductor is placed within ground shields having a fixed width.

摘要翻译： 描述了一种基于副本级构建时钟树的系统和方法。 系统和方法可以包括基于扇出来确定用于驱动输出缓冲器的负载电容的输入缓冲器的大小，基于输出缓冲器的大小，扇出和复制级确定线宽度和线长度 数学模型，以及将输出缓冲器和相应的输入缓冲器连接到在一个或多个预定金属层上布线并具有线长度和线宽度的导体。 导体放置在具有固定宽度的接地屏蔽内。

公开(公告)号：US08618840B1

公开(公告)日：2013-12-31

申请号：US13546702

申请日：2012-07-11

申请人： William W. Walker

发明人： William W. Walker

IPC分类号： H03B21/00

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1243 ,  H03B2200/0048 ,  H03L7/0891 ,  H03L7/102 ,  H03L2207/06

摘要： A frequency synthesizer circuit includes a phase determinator configured to output a phase difference signal based on a phase difference between an output signal and a reference signal. The frequency synthesizer circuit may further include a voltage controlled oscillator configured, during a fine tuning mode, to generate the output signal based on the phase difference signal and a value of a frequency band signal. The voltage controlled oscillator may be further configured, during a coarse tuning mode, to generate the output signal based on a voltage and the value of the frequency band signal. The frequency synthesizer circuit may further include a control unit configured to generate the frequency band signal. The value of the frequency band signal may be static during the fine tuning mode and changing during the coarse tuning mode based on a frequency difference between the reference signal and the output signal.

摘要翻译： 频率合成器电路包括：相位确定器，被配置为基于输出信号和参考信号之间的相位差来输出相位差信号。 频率合成器电路还可以包括在微调模式期间基于相位差信号和频带信号的值产生输出信号的压控振荡器。 压电振荡器还可以在粗调谐模式期间被配置为基于电压和频带信号的值产生输出信号。 频率合成器电路还可以包括被配置为产生频带信号的控制单元。 在微调模式期间，频带信号的值可以是静态的，并且基于参考信号和输出信号之间的频率差在粗调谐模式期间改变。

公开(公告)号：US06778466B2

公开(公告)日：2004-08-17

申请号：US10121968

申请日：2002-04-11

申请人： William W. Walker

发明人： William W. Walker

IPC分类号： G11C1304

CPC分类号： G11C8/16

摘要： An improved multi-port memory cell circuit which has a smaller number of write lines and/or transistors than conventional multi-port memory cells, and hence occupies a smaller area, is provided. The reduced area memory cell circuit includes: word lines associated with each bit line of a set of bit lines; a first word line for selecting a subset of the set of bit lines; a second word line for selecting a bit line of the subset of bit lines; and a memory cell for storing a bit value on the selected bit line.

摘要翻译： 提供了一种改进的多端口存储单元电路，其具有比常规多端口存储器单元更少数量的写入线和/或晶体管，因此占据较小的面积。 缩小面积存储单元电路包括：与一组位线的每个位线相关联的字线; 用于选择所述一组位线的子集的第一字线; 用于选择位线子集的位线的第二字线; 以及用于存储所选位线上的位值的存储单元。

公开(公告)号：US5987641A

公开(公告)日：1999-11-23

申请号：US18977

申请日：1998-02-05

申请人： William W. Walker

发明人： William W. Walker

IPC分类号： A41D13/08 ,  A63B71/14

CPC分类号： A41D13/088 ,  A63B71/14 ,  A63B2209/10

摘要： A wrist pad is provided including a flexible removable wrap with a top extent and a bottom extent. At least one sleeve is mounted on the bottom extent of the wrap. A rigid element includes at least one portion defining a periphery of a cylinder and a sphere. Such rigid element is removably situated within the sleeve during use.

摘要翻译： 提供了一种腕垫，其包括具有顶部范围和底部范围的柔性可移除的包裹物。 至少一个套筒安装在包装的底部范围上。 刚性元件包括限定圆柱体和球体的周边的至少一个部分。 这种刚性元件在使用期间可移除地位于套筒内。

公开(公告)号：US5130568A

公开(公告)日：1992-07-14

申请号：US609398

申请日：1990-11-05

申请人： Brent W. Miller ,  William W. Walker ,  Laurence H. Cooke

发明人： Brent W. Miller ,  William W. Walker ,  Laurence H. Cooke

IPC分类号： H03K3/037

CPC分类号： H03K3/0375

摘要： A scannable latch system comprises a plurality of scannable latches and clock driver circuit that allow at-speed testing of integrated circuits. Each scannable latch comprises a master latch, a slave latch and an auxiliary latch. The master latch is a two input latch capable of receiving data from two sources. The output of the master latch is coupled to the input of the slave and auxiliary latches. The clock driver circuitry receives a clock and control signals which are transformed into signals that operate the scannable latch in three different modes. In the normal mode, the slave latch is transparent and the data is held primarily in the master latch. In the scan mode, data may be shifted into the master, shifted out through the auxiliary latch, or shifted both in and out with a propagate function. Finally, in a test mode independent data values may be stored in the master latch and the slave latch.

摘要翻译： 可扫描闩锁系统包括允许集成电路的高速测试的多个可扫描锁存器和时钟驱动器电路。 每个可扫描锁存器包括主锁存器，从锁存器和辅助锁存器。 主锁存器是能够从两个源接收数据的两个输入锁存器。 主锁存器的输出端耦合到从锁存器和辅助锁存器的输入端。 时钟驱动器电路接收时钟和控制信号，这些信号被转换成以三种不同模式操作可扫描锁存器的信号。 在正常模式下，从锁存器是透明的，数据主要保存在主锁存器中。 在扫描模式下，数据可能被移入主器件，通过辅助锁存器移出，或者通过传播功能进入和移出。 最后，在测试模式下，独立的数据值可以存储在主锁存器和从锁存器中。