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公开(公告)号：US11315463B2
公开(公告)日：2022-04-26
申请号：US17052135
申请日：2019-08-08
Inventor： Xuehuan Feng , Yongqian Li
Abstract: A shift register includes an output sub-circuit, a cascade sub-circuit and at least one additional output sub-circuit. The output sub-circuit is configured to transmit a first clock signal received at the first clock signal terminal to the output signal terminal under control of a potential at the pull-up node, so as to scan a gate line coupled to the output signal terminal. The cascade sub-circuit is configured to transmit a second clock signal received at the second clock signal terminal to the cascade node under the control of the potential at the pull-up node. Each additional output sub-circuit is configured to transmit a clock signal received at a corresponding clock signal terminal to a corresponding additional output signal terminal under control of a potential at the cascade node, so as to scan a gate line coupled to the corresponding additional output signal terminal.
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公开(公告)号：US20220123056A1
公开(公告)日：2022-04-21
申请号：US17280725
申请日：2020-05-15
Inventor： Meng LI , Yongqian LI , Jingquan WANG , Chen XU , Dacheng ZHANG , Zhidong YUAN , Can YUAN , Xuehuan FENG
Abstract: A display region includes a plurality of pixel driving circuitry setting regions arranged sequentially in a first direction, and each pixel driving circuitry setting region extends in a second direction intersecting the first direction. Each display circuitry includes a plurality of subpixels in one-to-one correspondence with the pixel driving circuitry setting regions, each subpixel includes a subpixel driving circuitry and a light-emitting element coupled to each other, the subpixel driving circuitry is located in a corresponding pixel driving circuitry setting region, the light-emitting element is located at a side of the subpixel driving circuitry away from the substrate, a width of the light-emitting element is greater than a width of the corresponding pixel driving circuitry setting region in the first direction, and a length of the light-emitting element is smaller than a length of the corresponding pixel driving circuitry setting region in the second direction.
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公开(公告)号：US20220122529A1
公开(公告)日：2022-04-21
申请号：US17361549
申请日：2021-06-29
Inventor： Song MENG , Xuehuan FENG
IPC: G09G3/3225
Abstract: The present disclosure relates to the field of display technology, and describes a pixel driving circuit detection method, a display panel, a driving method thereof, and a display device. The detection method includes inputting a reference voltage to the data line during at least part of the initial phase; turning on the first and second switch sub-circuits during the charging phase, to input the detection voltage to the data line, while inputting the reset voltage to the sensing line; turning on the second switch sub-circuit during the charging phase, to input the driving current by the driving transistor to the sensing line under the effect of the detection voltage; turning off the first and second switch sub-circuits during the detection phase, to detect the voltage on the sensing line; and obtaining the mobility of the driving transistor according to the voltage on the sensing line detected in the detection phase.
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公开(公告)号：US20220101796A1
公开(公告)日：2022-03-31
申请号：US17427607
申请日：2021-01-22
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/3266 , G11C19/28
Abstract: A shift register, a gate driving circuit and a gate driving method are provided. The shift register includes: a display pre-charging reset circuit, a display noise reduction circuit and an output circuit, the output circuit is provided with at least one signal output terminal, and includes at least one output sub-circuit; the display pre-charging reset circuit is configured to write a first scanning voltage into a pull-up node in response to a control of a first signal input terminal; and write a second scanning voltage into the pull-up node in response to a control of a second signal input terminal; the display noise reduction circuit is configured to write the second scanning voltage into a pull-down node in response to the control of the first signal input terminal; and write the first scanning voltage into the pull-down node in response to the control of the second signal input terminal.
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公开(公告)号：US20220084457A1
公开(公告)日：2022-03-17
申请号：US17424483
申请日：2020-08-24
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/20
Abstract: The disclosure provides a shift register, a drive method thereof, a gate drive circuit, and a display panel. The shift register comprises a first shift register unit and a second shift register unit. The first shift register unit comprises a first input circuit, a first output circuit, a first pull-down circuit and a unidirectional isolation circuit, the first input circuit is connected to a first input terminal and a first pull-up node, the first output circuit is connected to the first pull-up node, a first output terminal and a first clock terminal, and the first output terminal is connected to the first pull-down circuit by means of the unidirectional isolation circuit; and the second shift register unit comprises a second input circuit and a second output circuit, the second input circuit is connected to a second input terminal and a second pull-up node, the second output circuit is connected to the second pull-up node, a second output terminal and a second clock signal, and the second output terminal is connected to a node between the first pull-down circuit and the unidirectional isolation circuit.
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Patent Agency Ranking
56.发明授权公开(公告)号：US11250784B2
公开(公告)日：2022-02-15
申请号：US16642469
申请日：2019-07-29
Inventor： Zhidong Yuan , Yongqian Li , Meng Li , Can Yuan
IPC: G09G3/3266 , G11C19/28
Abstract: The present disclosure discloses a shift register, a driving method thereof, a gate drive circuit, an array substrate and a display device. With a signal control circuit, a branch control circuit, a cascade signal output circuit and at least two scan signal output circuits, each shift register can output at least two scan signals to correspond to different gate lines in a display panel. This can reduce the number of shift registers in a gate drive circuit and the space occupied by the gate drive circuit and can achieve an ultra-narrow frame design, as compared with an existing shift register that can only output one scan signal. Moreover, as signals of different output control node do not influence each other, the output stability can also be improved.
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57.发明授权公开(公告)号：US11244630B2
公开(公告)日：2022-02-08
申请号：US17265226
申请日：2020-06-18
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G3/3266 , G09G3/3258 , G11C19/28
Abstract: A shift register unit, a gate driving circuit, a display device, and a method for controlling a shift register unit are provided. The shift register unit includes a first input sub-circuit, a second input sub-circuit, a first isolation sub-circuit, and a first output sub-circuit. The first input sub-circuit is configured to control a potential of a first node. The second input sub-circuit is configured to control a potential of a second node. The first isolation sub-circuit is configured to control conduction and interruption of electrical coupling between the first node and the second node. The first output sub-circuit is configured to output a grate driving signal in a display phase and output a compensation driving signal in a field blanking phase.
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公开(公告)号：US11244595B2
公开(公告)日：2022-02-08
申请号：US16957161
申请日：2019-08-08
Inventor： Xuehuan Feng , Yongqian Li
IPC: G09G5/00 , G09G3/20 , G09G3/3266 , G09G3/36 , G11C19/28
Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node in response to an input signal input; the first control circuit is configured to control a level of the second node in response to the input signal and the level of the first node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal; and the second output circuit is configured to output a second output signal at the second output terminal.
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公开(公告)号：US20220013060A1
公开(公告)日：2022-01-13
申请号：US17294690
申请日：2020-08-20
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/20
Abstract: A shift register and a drive method therefor, and a gate drive circuit. The shift register includes: an input sub-circuit, a detection control sub-circuit, an output sub-circuit, a first reset sub-circuit, and a pull-down sub-circuit. The detection control sub-circuit is respectively connected to a random detection signal end (OE), a signal input end (INPUT), a first clock signal end (CLKA), a first reset end (RST1), and a pull-up node (PU), and is configured to provide a signal of the first clock signal end (CLKA) for the pull-up node (PU) under the control of the signal input end (INPUT), the random detection signal end (OE), the first clock signal end (CLKA), and the first reset end (RST1).
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公开(公告)号：US20220005413A1
公开(公告)日：2022-01-06
申请号：US17294676
申请日：2020-08-07
Inventor： Zhidong YUAN , Xuehuan FENG , Yongqian LI , Can YUAN , Meng LI , Dongxu HAN
IPC: G09G3/3241 , G09G3/3266
Abstract: A pixel circuit and a driving method thereof, and a display device, the pixel circuit being configured to drive a light-emitting element and including: a node control sub-circuit, which is configured to provide a first node with a signal of a data signal end and provide a second node with a signal of a control signal end under the control of a first scanning end; a driving sub-circuit, which is configured to provide the second node with a driving current under the control of the first node and the second node; a storage sub-circuit, which is configured to store electric charge between the first node and the second node; a reading sub-circuit, and the light-emitting element, which is electrically connected to the second node and a second power supply end, respectively.
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