Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation
    51.
    发明申请
    Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation 有权
    在过程变化存在下生成具有匹配延迟的接线路由的方法

    公开(公告)号:US20080195993A1

    公开(公告)日:2008-08-14

    申请号:US12107158

    申请日:2008-04-22

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5077

    摘要: A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

    摘要翻译: 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始,或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径,例如第一布线路径,第二布线路径等。两条或多条布线路径被设计成具有匹配的定时,使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径,第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径,以使路径穿过大约相同长度的线段,并且 在第一布线路径和第二布线路径横越的各布线层内。 此外,该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。