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1.发明授权Method of generating wiring routes with matching delay in the presence of process variation 有权在存在过程变化的情况下生成具有匹配延迟的布线路线的方法公开(公告)号：US07418689B2
公开(公告)日：2008-08-26
申请号：US10908102
申请日：2005-04-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。
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公开(公告)号：US07401307B2
公开(公告)日：2008-07-15
申请号：US10904309
申请日：2004-11-03
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译： 公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。 通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。 对于每个独立参数重复此步骤。 然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。 然后将失败的定时终点根据其故障系数进行优先级修改。 所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。
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公开(公告)号：US07870525B2
公开(公告)日：2011-01-11
申请号：US12122451
申请日：2008-05-16
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译： 公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。 通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。 对于每个独立参数重复此步骤。 然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。 然后将失败的定时终点根据其故障系数进行优先级修改。 所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。
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公开(公告)号：US07716616B2
公开(公告)日：2010-05-11
申请号：US11930924
申请日：2007-10-31
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译： 公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。 通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。 对于每个独立参数重复此步骤。 然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。 然后将失败的定时终点根据其故障系数进行优先级修改。 所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。
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5.发明申请Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation 有权在过程变化存在下生成具有匹配延迟的接线路由的方法公开(公告)号：US20080195993A1
公开(公告)日：2008-08-14
申请号：US12107158
申请日：2008-04-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。
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公开(公告)号：US07962874B2
公开(公告)日：2011-06-14
申请号：US12183549
申请日：2008-07-31
IPC分类号： G06F17/50
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译： 用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。 该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。 使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。 在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。 本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。 在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。
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7.发明授权Method of generating wiring routes with matching delay in the presence of process variation 有权在存在过程变化的情况下生成具有匹配延迟的布线路线的方法公开(公告)号：US07865861B2
公开(公告)日：2011-01-04
申请号：US12107158
申请日：2008-04-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。
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公开(公告)号：US20080216036A1
公开(公告)日：2008-09-04
申请号：US12122451
申请日：2008-05-16
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
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公开(公告)号：US07089143B2
公开(公告)日：2006-08-08
申请号：US10709361
申请日：2004-04-29
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译： 用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。 该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。 使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。 在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。 本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。 在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。
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10.发明授权Method of generating wiring routes with matching delay in the presence of process variation 有权在存在过程变化的情况下生成具有匹配延迟的布线路线的方法公开(公告)号：US07823115B2
公开(公告)日：2010-10-26
申请号：US12108629
申请日：2008-04-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。
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