公开(公告)号：US08725918B2

公开(公告)日：2014-05-13

申请号：US13494179

申请日：2012-06-12

申请人： Anup K. Sharma ,  Scott P. Krueger ,  James M. Hollabaugh ,  Roberto G. Yepez ,  Mitchell D. Adler ,  Brijesh Tripathi ,  Jeffrey J. Terlizzi

发明人： Anup K. Sharma ,  Scott P. Krueger ,  James M. Hollabaugh ,  Roberto G. Yepez ,  Mitchell D. Adler ,  Brijesh Tripathi ,  Jeffrey J. Terlizzi

IPC分类号： G06F13/38 ,  G09G3/34

CPC分类号： G06F3/1431 ,  G06F3/14 ,  G06F13/385 ,  G06F13/4013 ,  G06F13/4018 ,  G06T1/60 ,  Y02D10/14 ,  Y02D10/151

摘要： In an embodiment, a host computing device includes an internal display and also includes a connector to connect to an external display. A cable is provided to connect to the connector and to connect to the external display. The cable includes video processing capabilities. For example, the cable may include a memory configured to store a frame buffer. The frame buffer may store a frame of video data for further processing by the video processing device in the cable. The video processing device may manipulate the frame in a variety of ways, e.g. scaling, rotating, gamma correction, dither correction, etc.

公开(公告)号：US20130223764A1

公开(公告)日：2013-08-29

申请号：US13404850

申请日：2012-02-24

申请人： Brijesh Tripathi ,  Nitin Bhargava ,  Craig M. Okruhlica

发明人： Brijesh Tripathi ,  Nitin Bhargava ,  Craig M. Okruhlica

IPC分类号： G06K9/32

CPC分类号： G06T3/4007

摘要： A parallel scaler unit for simultaneously scaling multiple pixels from a source image. The scaler unit includes multiple vertical scalers and multiple horizontal scalers. A column of pixels from the source image is presented to the vertical scalers, and each vertical scaler selects appropriate pixels from the column of pixels for scaling. Each vertical scaler scales the selected pixels in a vertical direction and then conveys the vertically scaled pixels to a corresponding horizontal scaler. Each horizontal scaler scales the received pixels in a horizontal direction.

摘要翻译： 一个并行缩放器单元，用于同时缩放源图像中的多个像素。 缩放器单元包括多个垂直缩放器和多个水平缩放器。 来自源图像的一列像素被呈现给垂直缩放器，并且每个垂直缩放器从用于缩放的像素列中选择合适的像素。 每个垂直缩放器在垂直方向上缩放所选择的像素，然后将垂直缩放的像素传送到相应的水平缩放器。 每个水平缩放器在水平方向上缩放接收到的像素。

公开(公告)号：US20130222411A1

公开(公告)日：2013-08-29

申请号：US13406856

申请日：2012-02-28

申请人： Brijesh Tripathi ,  Craig M. Okruhlica ,  John S. Harper ,  Steve Swen

发明人： Brijesh Tripathi ,  Craig M. Okruhlica ,  John S. Harper ,  Steve Swen

IPC分类号： G09G5/02 ,  G06K9/00

CPC分类号： H04N9/68

摘要： Techniques are disclosed relating to additive color systems. In one embodiment, an apparatus is disclosed that includes a device configured to operate on pixel data having color component values falling within an extended range outside of 0.0 to 1.0 corresponding to an extended range color space. In one embodiment, a gamma correction function is disclosed that can be applied to the pixel data, where the gamma correction function is applicable to both negative and positive values. Various embodiments of formats for arranging pixel data are also disclosed.

摘要翻译： 公开了与加色系统有关的技术。 在一个实施例中，公开了一种装置，其包括被配置为对具有落在与扩展范围颜色空间相对应的0.0至1.0之外的扩展范围内的颜色分量值的像素数据进行操作的装置。 在一个实施例中，公开了可以应用于像素数据的伽马校正功能，其中伽马校正功能适用于负值和正值两者。 还公开了用于布置像素数据的格式的各种实施例。

公开(公告)号：US20130002703A1

公开(公告)日：2013-01-03

申请号：US13238023

申请日：2011-09-21

申请人： Brijesh Tripathi ,  Craig M. Okruhlica ,  Wolfgang Roethig

发明人： Brijesh Tripathi ,  Craig M. Okruhlica ,  Wolfgang Roethig

IPC分类号： G09G5/02

CPC分类号： G09G5/04 ,  G09G3/2051 ,  G09G2320/0271

摘要： A dither unit with a programmable kernel matrix in which each indexed location/entry may store one or more dither values. Each dither value in a respective entry of the kernel matrix may correspond to the number of bits that are truncated during dithering. During dithering of each pixel of an image, entries in the kernel matrix may be indexed according to the relative coordinates of the pixel within the image. A dither value for the pixel may be selected from the indexed entry based on the truncated least significant bits of the pixel component value. When the kernel matrix is storing more than one dither value per entry, the dither value may be selected based further on the number of truncated least significant bits. A dithered pixel component value may then be generated according to the dither value and the remaining most significant bits of the pixel component value.

摘要翻译： 具有可编程内核矩阵的抖动单元，其中每个索引的位置/条目可以存储一个或多个抖动值。 内核矩阵的相应条目中的每个抖动值可以对应于在抖动期间被截断的位数。 在图像的每个像素的抖动期间，内核矩阵中的条目可以根据图像内的像素的相对坐标进行索引。 可以基于像素分量值的截断的最低有效位从索引条目中选择像素的抖动值。 当内核矩阵每个条目存储多于一个抖动值时，可以进一步基于截断的最低有效位的数量来选择抖动值。 然后可以根据抖动值和像素分量值的剩余最高有效位来产生抖动像素分量值。

公开(公告)号：US08165257B2

公开(公告)日：2012-04-24

申请号：US12321835

申请日：2009-01-26

申请人： Brijesh Tripathi

发明人： Brijesh Tripathi

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H04L25/14

摘要： A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a single first in first out (FIFO) buffer in each serial channel is described. The RapidIO® data channel, for example, operates using a clock recovered from the data stream. The RapidIO® data stream has embedded special characters, where a select sequence of embedded characters is a clock compensation pattern. A look ahead circuit is used to detect the clock compensation pattern early and generate a clock compensation indicator signal. The FIFO writes data and the associated clock compensation indicator signal in a clock compensation indicator bit in synchronism with the recovered clock. A read circuit using a second clock of a different frequency than the first clock reads data and clock compensation bits from the FIFO and generates an almost empty signal when appropriate. A multiplexer is used at the FIFO output to pad data to the system interface. A clock compensation control circuit generates a selection signal based on an AND of the almost empty signal and the clock compensation indicator bit associated with a data element read out of the FIFO and using the selection signal to control the multiplexer selection signal.

摘要翻译： 描述了在每个串行通道中使用单个先进先出（FIFO）缓冲器的数据流缓冲器管理，通道对准和时钟边界的数据传输的时钟补偿电路。 例如，RapidIO®数据通道使用从数据流恢复的时钟进行操作。 RapidIO®数据流嵌入了特殊字符，其中嵌入字符的选择顺序是时钟补偿模式。 使用前视电路提前检测时钟补偿模式，并产生时钟补偿指示信号。 FIFO与恢复的时钟同步地将数据和相关的时钟补偿指示符信号写入时钟补偿指示符位。 使用与第一时钟不同的频率的第二时钟的读取电路从FIFO读取数据和时钟补偿位，并在适当时产生几乎为空的信号。 在FIFO输出端使用多路复用器将数据填充到系统接口。 时钟补偿控制电路基于几乎为空的信号的AND和与从FIFO读出的数据元素相关联的时钟补偿指示符位产生选择信号，并使用选择信号来控制多路复用器选择信号。

公开(公告)号：US07515208B1

公开(公告)日：2009-04-07

申请号：US10962358

申请日：2004-10-08

申请人： Wayne Douglas Young ,  Brijesh Tripathi

发明人： Wayne Douglas Young ,  Brijesh Tripathi

IPC分类号： H03M1/12

CPC分类号： G09G5/006 ,  G09G2330/12 ,  G09G2370/04

摘要： Apparatus, system, and method for detecting AC-coupled electrical loads of a set of digital-to-analog converters are described. In one embodiment, a processing apparatus includes a digital-to-analog converter. The processing apparatus also includes a pulse generation module connected to the digital-to-analog converter, and the pulse generation module is configured to direct the digital-to-analog converter to transmit a pulse of electrical energy. The processing apparatus further includes a load detection module connected to the digital-to-analog converter, and the load detection module is configured to determine a connection status of the digital-to-analog converter based on a degree to which the pulse of electrical energy is reflected during a transient response time period.

摘要翻译： 描述了用于检测一组数模转换器的交流耦合电负载的装置，系统和方法。 在一个实施例中，处理装置包括数模转换器。 处理装置还包括连接到数模转换器的脉冲发生模块，并且脉冲发生模块被配置为引导数模转换器传送电能脉冲。 所述处理装置还包括连接到所述数模转换器的负载检测模块，并且所述负载检测模块被配置为基于所述数字模拟转换器的电能脉冲的程度来确定所述数模转换器的连接状态 在瞬态响应时间段内被反射。

公开(公告)号：US20060109929A1

公开(公告)日：2006-05-25

申请号：US10993542

申请日：2004-11-19

申请人： Brijesh Tripathi

发明人： Brijesh Tripathi

IPC分类号： H04L27/10

CPC分类号： H04L25/14

摘要： A circuit for data stream buffer management, lane alignment, and clock compensation of data transfers across a clock boundary using a single first in first out (FIFO) buffer in each serial channel is described. The RapidIO® data channel, for example, operates using a clock recovered from the data stream. The RapidIO® data stream has embedded special characters, where a select sequence of embedded characters is a clock compensation pattern. A look ahead circuit is used to detect the clock compensation pattern early and generate a clock compensation indicator signal. The FIFO writes data and the associated clock compensation indicator signal in a clock compensation indicator bit in synchronism with the recovered clock. A read circuit using a second clock of a different frequency than the first clock reads data and clock compensation bits from the FIFO and generates an almost empty signal when appropriate. A multiplexer is used at the FIFO output to pad data to the system interface. A clock compensation control circuit generates a selection signal based on an AND of the almost empty signal and the clock compensation indicator bit associated with a data element read out of the FIFO and using the selection signal to control the multiplexer selection signal.