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1.发明授权公开(公告)号：US08831161B2
公开(公告)日：2014-09-09
申请号：US13223214
申请日：2011-08-31
Applicant: Colin Whitby-Strevens , Moon Kim , Brijesh Tripathi , Geertjan Joordens
Inventor： Colin Whitby-Strevens , Moon Kim , Brijesh Tripathi , Geertjan Joordens
CPC classification number: G06F13/14 , H04L12/281 , Y02D10/14
Abstract: Methods and apparatus for adjusting the operation of a display device so as to be at least within prescribed form factor or other constraints. In one embodiment of the invention, various operational parameters for a display element are adjusted based on considerations specific to high density form factor constraints. For example, in one such device, a Low Power DisplayPort (LPDP) device having a LPDP source and sink adjust the data rate of the visual data to minimize power consumption while still properly supporting display panel resolutions. In some embodiments, the LPDP source and sink may adjust the transceiver voltages to minimize power consumption. In an alternate embodiment, an LPDP device adjusts data rates to minimize the effects of platform noise. In another aspect of the invention, various display elements of a device coordinate quiescent (“quiet”) mode operation during periods of inactivity.
Abstract translation: 用于调节显示装置的操作以至少在规定的形状因数或其他限制内的方法和装置。 在本发明的一个实施例中，用于显示元件的各种操作参数基于特定于高密度形状因子约束的考虑来调整。 例如，在一个这样的设备中，具有LPDP源和接收器的低功率显示端口（LPDP）设备调整视觉数据的数据速率以最小化功耗，同时仍然适当地支持显示面板分辨率。 在一些实施例中，LPDP源和接收器可以调整收发器电压以最小化功率消耗。 在替代实施例中，LPDP设备调整数据速率以最小化平台噪声的影响。 在本发明的另一方面，在不活动期间，设备坐标静止（“安静”）模式操作的各种显示元件。
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公开(公告)号：US20130057567A1
公开(公告)日：2013-03-07
申请号：US13226604
申请日：2011-09-07
Applicant: Michael Frank , Brijesh Tripathi , Peter F. Holland
Inventor： Michael Frank , Brijesh Tripathi , Peter F. Holland
IPC: G09G5/02
CPC classification number: G06F3/1454 , G09G2340/0407 , G09G2340/06
Abstract: The same pixel stream may be displayed on an internal display and an external display while maintaining the original aspect ratio corresponding to the internal display dimensions. A connector with limited number of pins may only support a two-wire display port interface to the external display, which may not provide enough bandwidth to transmit the full resolution image to the external display. To transmit the full resolution image, a color space conversion from RGB space to YCbCr color space may be performed. The Luma component may be transmitted at full resolution, while the chroma components may be scaled. Accordingly, there is no loss of image resolution, while some amount of color resolution may be lost. However, there is no need to retime frames within the system on chip (SOC), and the same pixel stream may be used as the basis for display on both the internal and the external display.
Abstract translation: 可以在内部显示器和外部显示器上显示相同的像素流，同时保持对应于内部显示器尺寸的原始宽高比。 具有有限数量引脚的连接器可能仅支持外部显示器的两线显示端口接口，这可能不能提供足够的带宽以将全分辨率图像传输到外部显示器。 为了传输全分辨率图像，可以执行从RGB空间到YCbCr颜色空间的颜色空间转换。 亮度分量可以以全分辨率传输，而色度分量可以被缩放。 因此，不会有图像分辨率的损失，而一些颜色分辨率可能会丢失。 然而，不需要在片上系统（SOC）内重新定时帧，并且可以使用相同的像素流作为在内部和外部显示器上显示的基础。
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公开(公告)号：US20120194530A1
公开(公告)日：2012-08-02
申请号：US13442790
申请日：2012-04-09
Applicant: Duncan A. RIACH , Michael A. Ogrinc , Brijesh Tripathi , Wayne D. Young
Inventor： Duncan A. RIACH , Michael A. Ogrinc , Brijesh Tripathi , Wayne D. Young
CPC classification number: G06T3/40 , G06T1/20 , G09G5/001 , G09G5/363 , G09G5/39 , G09G2340/0421 , G09G2352/00 , G09G2360/123
Abstract: One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitted to a video pipeline for processing. The resulting video pixel data is routed to video output encoders, which selectively accept the video pixel data for transmission to attached display devices.
Abstract translation: 本发明的一个实施例提出了一种用于从图形处理单元内的单个视频流水线生成多个视频输出信号的系统。 在将多个显示表面的像素数据发送到视频流水线进行处理之前被检索和多路复用。 所得到的视频像素数据被路由到视频输出编码器，其选择性地接受视频像素数据以传输到附接的显示设备。
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公开(公告)号：US09652194B2
公开(公告)日：2017-05-16
申请号：US13494169
申请日：2012-06-12
Applicant: Anup K. Sharma , Scott P. Krueger , James M. Hollabaugh , Roberto G. Yepez , Brijesh Tripathi , Jeffrey J. Terlizzi
Inventor： Anup K. Sharma , Scott P. Krueger , James M. Hollabaugh , Roberto G. Yepez , Brijesh Tripathi , Jeffrey J. Terlizzi
CPC classification number: G06F3/1431 , G06F3/14 , G06F13/385 , G06F13/4013 , G06F13/4018 , G06T1/60 , Y02D10/14 , Y02D10/151
Abstract: In an embodiment, a host computing device includes an internal display and also includes a connector to connect to an external display. A cable is provided to connect to the connector and to connect to the external display. The cable includes video processing capabilities. For example, the cable may include a memory configured to store a frame buffer. The frame buffer may store a frame of video data for further processing by the video processing device in the cable. The video processing device may manipulate the frame in a variety of ways, e.g. scaling, rotating, gamma correction, dither correction, etc.
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公开(公告)号：US09035961B2
公开(公告)日：2015-05-19
申请号：US13610633
申请日：2012-09-11
Applicant: Brijesh Tripathi , Peter F. Holland
Inventor： Brijesh Tripathi , Peter F. Holland
CPC classification number: G06F12/0888 , G06F2212/455 , G09G5/001 , G09G5/363 , G09G5/39 , G09G5/395 , G09G2360/121 , G09G2360/123
Abstract: A system and method for efficiently allocating data in a memory hierarchy. A system includes a memory controller for controlling accesses to a memory and a display controller for processing video frame data. The memory controller includes a cache capable of storing data read from the memory. A given video frame may be processed by the display controller and presented on a respective display screen. During processing, control logic within the display controller sends multiple memory access requests to the memory controller with cache hint information. For the frame data, the cache hint information may alternate between (i) indicating to store frame data read in response to respective requests in the memory cache and (ii) indicating to not store the frame data read in response to respective requests in the memory cache.
Abstract translation: 一种用于在存储器层级中有效分配数据的系统和方法。 系统包括用于控制对存储器的访问的存储器控制器和用于处理视频帧数据的显示控制器。 存储器控制器包括能够存储从存储器读取的数据的高速缓存器。 给定的视频帧可以由显示控制器处理并呈现在相应的显示屏幕上。 在处理期间，显示控制器内的控制逻辑使用高速缓存提示信息向存储器控制器发送多个存储器访问请求。 对于帧数据，缓存提示信息可以在（i）指示存储响应于存储器高速缓存中的相应请求而读取的帧数据和（ii）指示不存储响应于存储器中的各个请求而读取的帧数据的交替 缓存。
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Patent Agency Ranking
公开(公告)号：US09015217B2
公开(公告)日：2015-04-21
申请号：US13435900
申请日：2012-03-30
Applicant: Vaughn T. Arnold , Brijesh Tripathi , Albert Kuo
Inventor： Vaughn T. Arnold , Brijesh Tripathi , Albert Kuo
CPC classification number: G06F7/544 , G06F1/03 , G06F1/0307 , G06F1/0356 , G06F2101/08 , G06F2101/12
Abstract: In an embodiment, hardware implementing a transcendental or other non-linear function is based on a series expansion of the function. For example, a Taylor series expansion may be used as the basis. One or more of the initial terms of the Taylor series may be used, and may be implemented in hardware. In some embodiments, modifications to the Taylor series expansion may be used to increase the accuracy of the result. In one embodiment, a variety of bit widths for the function operands may be acceptable for use in a given implementation. A methodology for building a library of series-approximated components for use in integrated circuit design is provided which synthesizes the acceptable implementations and tests the results for accuracy. A smallest (area-wise) implementation which produces a desired level of accuracy may be selected as the library element.
Abstract translation: 在一个实施例中，实现先验或其他非线性函数的硬件基于功能的一系列扩展。 例如，可以使用泰勒级数展开作为基础。 可以使用泰勒级数的一个或多个初始项，并且可以以硬件实现。 在一些实施例中，可以使用对泰勒级数展开的修改来提高结果的准确性。 在一个实施例中，功能操作数的各种位宽可以被接受以用于给定的实现。 提供了一种用于构建用于集成电路设计的串联近似组件库的方法，其综合了可接受的实现并且测试结果的准确性。 可以选择产生所需精度水平的最小（区域）实现作为库元件。
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公开(公告)号：US08860750B2
公开(公告)日：2014-10-14
申请号：US13043183
申请日：2011-03-08
Applicant: Brijesh Tripathi , Michael Frank
Inventor： Brijesh Tripathi , Michael Frank
IPC: G09G5/00 , G09G5/02 , G06K9/40 , H03L7/00 , H04N7/00 , H03M1/12 , H04N1/46 , G06K15/00 , G06K9/38 , G06K9/60 , G09G3/20
CPC classification number: G09G3/2037 , G09G3/2051 , G09G3/2066 , G09G2320/0266
Abstract: Devices and methods for dynamic dithering are provided. For example, an electronic device according to an embodiment may include image processing circuitry that operates on higher-bit-depth image data and a display panel that displays lower-bit-depth image data. To obtain the lower-bit-depth image data, the image processing circuitry may perform dynamic dithering on the higher-bit-depth image data. Such dynamic dithering may involve dithering frames of the higher-bit-depth image data based at least in part on respective rounding threshold values.
Abstract translation: 提供动态抖动的设备和方法。 例如，根据实施例的电子设备可以包括对高位深度图像数据进行操作的图像处理电路和显示低位深度图像数据的显示面板。 为了获得低位深度图像数据，图像处理电路可以对高位深度图像数据执行动态抖动。 这种动态抖动可以至少部分地基于相应的舍入阈值来涉及高位深度图像数据的抖动帧。
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公开(公告)号：US20140071140A1
公开(公告)日：2014-03-13
申请号：US13610620
申请日：2012-09-11
Applicant: Brijesh Tripathi , Peter F. Holland , Shing Horng Choo , Steven T. Peltier
Inventor： Brijesh Tripathi , Peter F. Holland , Shing Horng Choo , Steven T. Peltier
Abstract: A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode.
Abstract translation: 一种用于有效地调度存储器访问请求的系统和方法。 半导体芯片包括用于控制对共享存储器的访问的存储器控制器和用于处理帧数据的显示控制器。 响应于检测到系统和所支持的一个或多个显示器的空闲状态，显示控制器在尝试将来自给定显示管道的任何存储器请求发送到所述显示管道之前对一个或多个显示管道的给定显示管线集合存储器请求 内存控制器 可以在给定的显示管道发送聚合的存储器请求时执行仲裁。 响应于不接收来自功能块或显示控制器的存储器访问请求，存储器控制器可以转换到低功率模式。
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公开(公告)号：US08644782B2
公开(公告)日：2014-02-04
申请号：US13435033
申请日：2012-03-30
Applicant: Brijesh Tripathi , Timothy J. Millet
Inventor： Brijesh Tripathi , Timothy J. Millet
IPC: H04B7/00
Abstract: A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface.
Abstract translation: 公开了一种用于改变时钟信号的频率以避免干扰的方法和装置。 在一个实施例中，在第一接口上传送的数据与第一频率的时钟信号同步。 信号在另一个频率的第二个接口上传送。 响应于在第二接口上传送信号的频率的变化，与第一接口相关联的时钟控制单元启动时钟信号的变化到第二频率。 第二频率可以被选择为不引起对在第二接口上传送信号的频率的干扰。 时钟频率的改变可以以防止对接口的时钟线的虚假活动的方式来执行。
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公开(公告)号：US20130120037A1
公开(公告)日：2013-05-16
申请号：US13435033
申请日：2012-03-30
Applicant: Brijesh Tripathi , Timothy J. Millet
Inventor： Brijesh Tripathi , Timothy J. Millet
IPC: H03L7/08
Abstract: A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface.
Abstract translation: 公开了一种用于改变时钟信号的频率以避免干扰的方法和装置。 在一个实施例中，在第一接口上传送的数据与第一频率的时钟信号同步。 信号在另一个频率的第二个接口上传送。 响应于在第二接口上传送信号的频率的变化，与第一接口相关联的时钟控制单元启动时钟信号的变化到第二频率。 第二频率可以被选择为不引起对在第二接口上传送信号的频率的干扰。 时钟频率的改变可以以防止对接口的时钟线的虚假活动的方式来执行。
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