公开(公告)号：US20150003575A1

公开(公告)日：2015-01-01

申请号：US14321390

申请日：2014-07-01

Applicant: ESS Technology, Inc.

Inventor： A. Martin Mallinson

IPC: H04L7/00

CPC classification number: H03H17/06 ,  H03H17/0229 ,  H03H17/0248 ,  H03H17/0286 ,  H03H17/0294 ,  H03H21/0012 ,  H03H21/002

Abstract: FIR filters for compensating for fixed pattern jitter, and methods of constructing the same, are disclosed. In one embodiment, a FIR filter filters a signal having a desired frequency component, with the coefficients of the FIR filter selected so that the filter is the equivalent of two combined FIR filters, one having the desired frequency at the filter's peak output frequency, and a second in which the signal is delayed by a time equal to half of a period of a different frequency which is desired to be removed from the on signal. In another embodiment, a FIR filter includes a delay line with a total delay longer than the period of the jitter. A signal is passed down the delay line, the number of signal edges that have occurred as the signal passes each delay element in the counted. Drivers corresponding to the delay elements in which a number of signal edges occur at the desired frequency during the period of fixed pattern jitter activate impedance elements attached to those delay elements. A processor configures the activated impedance elements to provide the desired filter response.

Abstract translation: 公开了用于补偿固定模式抖动的FIR滤波器及其构造方法。 在一个实施例中，FIR滤波器对具有期望频率分量的信号进行滤波，其中选择FIR滤波器的系数，使得滤波器等效于两个组合的FIR滤波器，一个具有滤波器峰值输出频率处的期望频率， 其中信号被延迟等于期望从接通信号去除的不同频率的周期的一半的时间的第二。 在另一个实施例中，FIR滤波器包括具有比抖动周期长的总延迟的延迟线。 信号沿着延迟线传递，当信号通过计数的每个延迟元件时，发生的信号边沿的数量。 对应于在固定模式抖动的周期期间以期望频率出现的信号边缘数量的延迟元件的驱动器激活连接到这些延迟元件的阻抗元件。 处理器配置激活的阻抗元件以提供期望的滤波器响应。

公开(公告)号：US20140105269A1

公开(公告)日：2014-04-17

申请号：US14055785

申请日：2013-10-16

Applicant: ESS Technology, Inc.

Inventor： A. Martin Mallinson

IPC: H04L25/49

CPC classification number: H04L25/4902 ,  H03H17/0213 ,  H03H17/06

Abstract: A system and method for filtering an analog signal with a finite impulse response (FIR) filter that does not require analog delay elements are disclosed. An analog signal is pulse-width encoded, and the pulse-width encoded signal passed to a delay line comprising unclocked delay elements, such as logic gates, rather than clocked delay elements such as are used in conventional FIR filters. The propagation of the input signal is thus due only to the delay inherent in each gate, and occurs based upon when a signal reaches the gate rather than being caused by a clock signal. As with a conventional FIR filter, weighting elements having impedance are used to weigh the output of each delay element, and the resulting outputs summed to obtain a filtered output signal. For certain signals, such a circuit and method provides a simpler way of filtering than conventional filters.

Abstract translation: 公开了一种使用不需要模拟延迟元件的有限脉冲响应（FIR）滤波器对模拟信号进行滤波的系统和方法。 模拟信号被脉冲宽度编码，并且脉冲宽度编码信号传递到包括诸如逻辑门之类的非锁定延迟元件的延迟线，而不是例如在常规FIR滤波器中使用的定时延迟元件。 因此，输入信号的传播仅由于每个栅极固有的延迟而发生，并且基于何时信号到达门而不是由时钟信号引起。 与常规FIR滤波器一样，具有阻抗的加权元件用于称量每个延迟元件的输出，并且所得到的输出相加以获得经滤波的输出信号。 对于某些信号，这种电路和方法提供比常规滤波器更简单的滤波方式。

公开(公告)号：US20140073279A1

公开(公告)日：2014-03-13

申请号：US14022155

申请日：2013-09-09

Applicant: ESS Technology, Inc.

Inventor： Robert Lynn Blair ,  A. Martin Mallinson

IPC: H04B1/26

CPC classification number: H04B1/26 ,  H04B1/0007

Abstract: A method and system is disclosed for simultaneously down-converting multiple selected signals, such as RF signals, into adjacent ranges in an intermediate frequency band so that the total resulting bandwidth, and thus the sampling rate required to digitize the signal, is minimized. A first signal is down-converted into a range starting at a lowest selected frequency in the IF band. The next signal is down-converted, into a range higher than, but near or adjacent to, the down-converted range of the first signal, and so on. A guard band may be left between the signals if desired. In this way, the selected signals occupy the minimum bandwidth required. When the selection of signals to be down-converted is changed, the frequency ranges are dynamically adjusted so that the signals being down-converted always occupy the lowest ranges of the IF band.

Abstract translation: 公开了一种方法和系统，用于同时将多个所选信号（例如RF信号）下变频到中间频带中的相邻范围，使得总结果带宽以及因此将信号数字化所需的采样率最小化。 第一信号被下变频到从IF频段中最低选定频率开始的范围。 下一个信号被降频转换成高于第一信号的下变频范围但接近或相邻的范围，等等。 如果需要，保护带可能会留在信号之间。 以这种方式，所选择的信号占用所需的最小带宽。 当要降低转换的信号的选择被改变时，动态地调节频率范围，使得被降频转换的信号总是占据IF频带的最低范围。

公开(公告)号：US20130254253A1

公开(公告)日：2013-09-26

申请号：US13848272

申请日：2013-03-21

Applicant: ESS TECHNOLOGY, INC.

Inventor： A. Martin Mallinson

IPC: G06G7/02

CPC classification number: G06G7/02 ,  G06G7/625 ,  H03H15/023

Abstract: A circuit that provides a rotating coefficient FIR filter with all necessary coefficient sets present at the same time, without the need for delay elements, devices providing for adjustable impedances, or buffers is described. An input signal is sampled in a round robin fashion by a plurality of switches and capacitors. The capacitors are connected directly to sets of impedance devices. Each set of impedance devices implements the coefficients of the desired frequency response of the filter, adjusted to compensate for the decay of samples in the capacitors between samples. The impedance devices in each set are connected to the capacitors in a different order from each other set, so that each set of impedance devices will produce the desired frequency response when a different one of the capacitor contains a new sample of the input signal. Switches connect the sets of impedance devices to an output and a virtual ground, only one switch being connected to the output at a time to provide the output signal.

Abstract translation: 描述了提供具有同时存在的所有必要系数组的旋转系数FIR滤波器的电路，而不需要延迟元件，提供可调节阻抗的装置或缓冲器。 通过多个开关和电容器以循环方式对输入信号进行采样。 电容器直接连接到一组阻抗器件上。 每组阻抗器件实现滤波器所需频率响应的系数，被调整以补偿样本之间的电容器中样本的衰减。 每组中的阻抗器件以彼此不同的顺序连接到电容器，使得当电容器中的不同电容器包含输入信号的新采样时，每组阻抗器件将产生所需的频率响应。 开关将阻抗器件组连接到输出和虚拟接地，一次只有一个开关连接到输出端以提供输出信号。