公开(公告)号：US10971394B2

公开(公告)日：2021-04-06

申请号：US16284568

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Todd R. Younkin ,  Eungnak Han ,  Jasmeet S. Chawla ,  Marie Krysak ,  Hui Jae Yoo ,  Tristan A. Tronic

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US10950501B2

公开(公告)日：2021-03-16

申请号：US15772013

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Todd R. Younkin ,  Eungnak Han ,  Shane M. Harlson ,  James M. Blackwell

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  G03F7/00 ,  G03F7/004 ,  G03F7/16 ,  H01L21/027

Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive. The method also includes irradiating and developing select locations of the third segregated block component to provide via openings over the metal lines of the lower metallization layer.