公开(公告)号：US10374793B2

公开(公告)日：2019-08-06

申请号：US15374700

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Sanu Mathew ,  Mark Anders ,  Jesse Walker ,  Jason Sandri

IPC: H04L9/06 ,  G06F12/14 ,  G06F17/50

Abstract: An instruction and logic for a Simon-based hashing for validation are described. In one embodiment, a processor comprises: a memory the memory to store a plurality of values; and a hash circuit comprising a Simon cipher circuit operable to receive the plurality of values from the memory, to apply a Simon cipher, and to generate an output for each of the plurality of values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values into a hash digest that is indicative of whether the values in the memory are valid.

公开(公告)号：US20190199517A1

公开(公告)日：2019-06-27

申请号：US16288536

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

IPC: H04L9/06

CPC classification number: H04L9/0637 ,  H04L9/065

Abstract: An integrated circuit features technology for generating a keystream. The integrated circuit comprises a cipher block with a linear feedback shift register (LFSR) and a finite state machine (FSM). The LFSR and the FSM are configured to generate a stream of keys, based on an initialization value and an initialization key. The FSM comprises an Sbox that is configured to use a multiplicative mask to mask data that is processed by the Sbox when the LFSR and the FSM are generating the stream of keys. Other embodiments are described and claimed.

公开(公告)号：US09843441B2

公开(公告)日：2017-12-12

申请号：US14035508

申请日：2013-09-24

Applicant: Intel Corporation

Inventor： Sanu Mathew ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

IPC: H04L9/28 ,  H04L9/06

CPC classification number: H04L9/0631 ,  H04L2209/24

Abstract: Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.