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    INTEGRATED CLOCK GATE WITH CIRCUITRY TO FACILITATE CLOCK FREQUENCY DIVISION
    1.
    发明公开
    INTEGRATED CLOCK GATE WITH CIRCUITRY TO FACILITATE CLOCK FREQUENCY DIVISION 审中-公开

    公开(公告)号：US20240007087A1

    公开(公告)日：2024-01-04

    申请号：US17856887

    申请日：2022-07-01

    Applicant: Intel Corporation

    Inventor： Steven Hsu ,  Amit Agarwal ,  Simeon Realov ,  Mark Anders ,  Ram Krishnamurthy

    IPC: H03K3/037 ,  H03K19/21 ,  G06F1/06

    CPC classification number: H03K3/037 ,  H03K19/21 ,  G06F1/06

    Abstract: Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.

    In-memory analog neural cache
    5.
    发明授权
    In-memory analog neural cache 有权

    公开(公告)号：US11502696B2

    公开(公告)日：2022-11-15

    申请号：US16160800

    申请日：2018-10-15

    Applicant: Intel Corporation

    Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

    IPC: H03M1/00 ,  H03M1/12 ,  G06N3/063 ,  G06N3/04 ,  G06N3/08

    Abstract: Embodiments are directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture (“PISA”) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements. Thus, the systems and methods described herein beneficially leverage the existing capabilities of on-chip SRAM processor memory circuitry to perform a relatively large number of analog vector/tensor calculations associated with execution of a neural network, such as a recurrent neural network, without burdening the processor circuitry and without significant impact to the processor power requirements.

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